# title
Arm C1-Pro Core MP203 Software Developer Errata Notice

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Arm® C1-Pro Core MP203 Software Developer Errata Notice

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3785504 The core might deadlock or prevent other cores from progressing when executing in Streaming SVE mode

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3309200 A load instruction might violate barrier-ordered-before requirements and observe stale data

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4689344 The CNT_CYCLES event can have a significant increment error due to WFE/WFI

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4656709 TRBE trigger mode does not respect TRBSR_EL1.TRG

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4402129 The TRBE forces wrong padding data during ETE draining, which corrupts the ETE trace

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4193714 TLBI+DSB might fail to ensure completion of memory accesses related to SME

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4075482 A SPE synchronisation event might not be respected if SPE is being disabled and a record can be saved to the buffer once re-enabled

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3918989 Power transition might deadlock on Utility Bus or APB access

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3806276 Clock is not gated in synchronous configurations when in FULL_RET power mode

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3773617 Read of ICH_VMCR_EL2.VBPR1 might return incorrect data based on SCR_EL3.NS

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3715659 Incorrect SME priority computation by the core when SCR_EL3.HXEN = 0

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3706576 Memory read effect crossing a 64B boundary might cause data corruption

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3694158 DSB ST instructions might not properly order younger loads

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3686597 Powerdown transition might deadlock

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3684268 Unprivileged data memory-dependent prefetches might leak privileged data

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3679375 Core can take spurious interrupt

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3649107 Read of ICV_RPR_EL1 group priority field might return incorrect data for an interrupt with NMI priority

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3646317 Some Trace Unit configurations might prevent forward progress

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3640337 MMU might send translation response to incorrect CME unit

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3619847 32B unaligned STR predicate or multiple-structure store instruction might cause the core to deadlock

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3362007 Store-exclusive instructions might cause data corruption or deadlock

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3338470 MSR PSTATE.SSBS to 0 is not fully self-synchronizing

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3336789 TBRE might write to memory for which it does not have write permissions

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3300099 Read of ICH_VMCR_EL2.VBPR1 might return incorrect data based on SCR_EL3.NS

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4679315 SPE PMSEVFR_EL1 allows writes to RAZ/WI bits [15:13]

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4646886 PMU event counters for CME events might count incorrectly after programming through the external interface

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4554302 Continuous ELA trigger activity might prevent core power down

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4440267 DC GVA instructions might update allocation tags twice

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4185290 Some PMU events might have incorrect values

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4106079 ETE and ELA timestamps are not accurate for core

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4100865 Incorrect behavior under WARM_RESET power mode

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3966817 AMU auxiliary (group 1) counters 4 and 5 are not counting when PMU is disabled

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3960887 The core might deadlock after leaving WARM_RST, DBG_RECOV, or OFF_EMU power modes

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3958342 A continuous flow of TLB invalidation instructions might prevent an uncacheable Streaming SVE store from becoming visible in finite time

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3892060 PMU events PMU_OVFS is always increased when PMCCNTR_EL0 overflows, independently of PMINTENSET_EL1.C value

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3803142 CPYM*/ CPYFM*/ SETGM*/ SETM* located at PC 0x0000fffffffffffc generates an invalid ELR at the end of the sequence

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3784345 Mismatch on PMSIDR_EL1.SME when FEAT_SME is implemented

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3774589 PMU events ASE_INST_SPEC and VFP_SPEC do not count for instructions executed in Streaming SVE Mode

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3765598 The PE deadlocks during the OFF state transition due to a Debug Halt Trigger command

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3730431 PMU cycle counter does not freeze on SPE event when MDCR_EL2.HPMN == 0

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3723701 FEAT_SPE_SME: events 24 and 25 are swapped

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3705602 ICH_LR<n>_EL2.NMI might incorrectly designate NMI for a Group 0 virtual interrupt

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3705601 VSET.priority might incorrectly designate non-maskable property (NMI)

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3694611 PMU counters might take wrong values when events are generated from the CME unit

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3632008 EDSCR.STATUS not updated on Halting Step when a Load-Exclusive instruction generates a synchronous exception

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3629257 Some PMU events might have incorrect values

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3623695 Store instruction might deadlock in case of external abort

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3611368 SP-unaligned SVE/SME instruction might cause the core to deadlock

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3602916 ELA Trigger signal does not match documented behavior

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3549647 PMU counters might take wrong values when events are generated from the CME unit

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3532706 Debug halting request not taken immediately after ERET

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3445225 PSTATE.{PAN,UAO} synchronization might not be honored while MSR PSTATE is speculative

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3348958 ESR.IESB can have an incorrect value on SError

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3336782 TRBIRQ is incorrectly masked when TRBLIMITR_EL1.E = 0

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3224883 PMU events might not be sent to trace unit in Streaming SVE mode

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3204536 Injected Error can wrongly update Error Record Register

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3195198 Setting CPUECTLR2_EL1[11] can cause deadlock

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.