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Arm Cortex-A720AE Core MP170 Software Developer Errata Notice

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Arm® Cortex®-A720AE Core MP170 Software Developer Errata Notice

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4410497 The TRBE forces wrong padding data during ETE draining, which corrupts the ETE trace

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3919728 Power transition might deadlock on Utility Bus or APB access

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3915924 SPE might overwrite current SPE records and fail to overwrite old SPE records

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3711913 DSB ST instructions might not properly order younger loads

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3699562 Read of ICH_VMCR_EL2.VBPR1 might return incorrect data based on SCR_EL3.NS

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3645545 TBRE might write to memory for which it does not have write permissions

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3456103 MSR PSTATE.SSBS to 0 is not fully self-synchronizing

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4491858 DC GVA instructions might update allocation tags twice

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4106554 ETE and ELA timestamps are not accurate for core

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3960891 The core might deadlock after leaving WARM_RST, DBG_RECOV, or OFF_EMU power modes

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3655257 ESR.IESB can have an incorrect value on SError

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3655077 PSTATE.{PAN,UAO} synchronization might not be honored while MSR PSTATE is speculative

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3637713 EDSCR.STATUS not updated on Halting Step when a Load-Exclusive instruction generates a synchronous exception

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3522596 TRBIRQ is incorrectly masked when TRBLIMITR_EL1.E = 0

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3132559 Checked stores in precise mode might fail to report tag check fails

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3132558 A continuous flow of snoops and other instructions might prevent a store from becoming visible in finite time

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3120195 SVE first faulting load crossing a 64B boundary might silently corrupt data in case of double external abort

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.