# title
Arm Cortex-A725 Core MP190 Software Developer Errata Notice

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Arm® Cortex®-A725 Core MP190 Software Developer Errata Notice

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3114823 LDP instructions crossing a 64B boundary might return corrupted data

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4656708 TRBE trigger mode does not respect TRBSR_EL1.TRG

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4410499 The TRBE forces wrong padding data during ETE draining, which corrupts the ETE trace

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3821522 The CNT_CYCLES event can have a significant increment error due to WFE/WFI

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3711914 DSB ST instructions might not properly order younger loads

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3699564 Read of ICH_VMCR_EL2.VBPR1 might return incorrect data based on SCR_EL3.NS

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3645547 TBRE might write to memory for which it does not have write permissions

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3456106 MSR PSTATE.SSBS to 0 is not fully self-synchronizing

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2936490 Load crossing a 64B boundary might cause data corruption

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2874943 Enabling the Statistical Profiling Extension might lead to deadlock

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4679314 SPE PMSEVFR_EL1 allows writes to RAZ/WI bits [15:13]

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4554301 Continuous ELA trigger activity might prevent core power down

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4491859 DC GVA instructions might update allocation tags twice

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4106550 ETE and ELA timestamps are not accurate for core

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3964442 STALL_BACKEND and CPU_CYCLE related PMU events increment during snoop handling in WFx state

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3960909 Core might deadlock after leaving WARM_RST, DBG_RECOV or OFF_EMU power modes

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3655259 ESR.IESB can have an incorrect value on SError

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3655079 PSTATE.{PAN,UAO} synchronization might not be honored while MSR PSTATE is speculative

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3637717 EDSCR.STATUS not updated on Halting Step when a Load-Exclusive instruction generates a synchronous exception

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3522600 TRBIRQ is incorrectly masked when TRBLIMITR_EL1.E = 0

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3080099 SVE first faulting load crossing a 64B boundary might silently corrupt data in case of double external abort

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3052872 Some PMU events might have incorrect values

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2930653 Some PMU events might have incorrect values

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2861078 Checked stores in precise mode might fail to report tag check fails

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.