# title
Arm Cortex-A520 Core (MP144) Software Developer Errata Notice

# topic.label
Arm® Cortex-A520 Core (MP144) Software Developer Errata Notice

# topic.topics[].topics[].topics[].label
2389819 TLB not invalidated in complex power transitions

# topic.topics[].topics[].topics[].label
2489489 Atomic instructions might use older allocation tag for tag check

# topic.topics[].topics[].topics[].label
2630792 Data corruption might occur during core powerdown

# topic.topics[].topics[].topics[].label
2655133 Core might deadlock during transition from ON to OFF, or ON to OFF_EMU power mode

# topic.topics[].topics[].topics[].label
2658327 BFMMLA instructions might produce incorrect result

# topic.topics[].topics[].topics[].label
2677201 MTE check for store might not observe correct memory ordering

# topic.topics[].topics[].topics[].label
2680753 A core might deadlock during powerdown if TRBE is enabled

# topic.topics[].topics[].topics[].label
2738620 Deferred error might become uncontainable

# topic.topics[].topics[].topics[].label
2858100 Core may deadlock due to an ECC error in L1 data cache

# topic.topics[].topics[].topics[].label
2938996 Data corruption or deadlock might happen if TRBE is enabled

# topic.topics[].topics[].topics[].label
2966298 A speculatively executed unprivileged load might leak privileged data via a cache side channel

# topic.topics[].topics[].topics[].label
3189100 Unmodified MTE tags might be written back to memory

# topic.topics[].topics[].topics[].label
3559261 Power transition to FULL_RET is denied if FUNC_RET is also enabled

# topic.topics[].topics[].topics[].label
3631357 Store operations might modify data twice

# topic.topics[].topics[].topics[].label
3672344 CPU non-secure physical timer event interrupt might be triggered incorrectly

# topic.topics[].topics[].topics[].label
3685825 CAS/CASP atomic instruction might get data corruption under certain conditions

# topic.topics[].topics[].topics[].label
3802428 Complex power transition might deadlock when a Utility bus or Debug APB access is sent to a core

# topic.topics[].topics[].topics[].label
3975966 Power transition might deadlock on Utility Bus or APB access

# topic.topics[].topics[].topics[].label
4491980 Faulting load might disclose data from previous load through side channel

# topic.topics[].topics[].topics[].label
4615642 Core power transition from OFF to ON might lead to deadlock

# topic.topics[].topics[].topics[].label
2441013 Completion of affected memory accesses might not be guaranteed by completion of a TLBI

# topic.topics[].topics[].topics[].label
2487790 ERR0MISC1 value might be incorrect after multiple simultaneous errors detected

# topic.topics[].topics[].topics[].label
2567050 Double-bit errors in the duplicate L1 data cache tag RAMs might lead to loss of coherency or deadlock

# topic.topics[].topics[].topics[].label
2572702 ELADISABLE does not disable APB access to the complex ELA

# topic.topics[].topics[].topics[].label
2604637 PMU event counts might be inaccurate

# topic.topics[].topics[].topics[].label
2626173 ERR0STATUS.SERR might be incorrect

# topic.topics[].topics[].topics[].label
2626511 Minimum power policy might prevent power off when FUNC_RET in use

# topic.topics[].topics[].topics[].label
2628441 External aborts might result in a deadlock

# topic.topics[].topics[].topics[].label
2637415 Core might not execute any instruction when performing Halting Step

# topic.topics[].topics[].topics[].label
2640950 External 32-bit writes to some 64-bit RAS registers are not mapped correctly

# topic.topics[].topics[].topics[].label
2668978 External aborts reporting cannot be disabled

# topic.topics[].topics[].topics[].label
2679529 Multiple simultaneous errors report for L1 data cache might be incorrect

# topic.topics[].topics[].topics[].label
2681778 TLBI not fully invalidating entries because of parity errors

# topic.topics[].topics[].topics[].label
2690489 Some architectural PMU events are not always available to trace unit

# topic.topics[].topics[].topics[].label
2708967 Read value of PMMIR is incorrect

# topic.topics[].topics[].topics[].label
2710075 Read value of IMP_CPUCFR_EL1 might be incorrect

# topic.topics[].topics[].topics[].label
2713358 ERRxSTATUS.UET field might be incorrect

# topic.topics[].topics[].topics[].label
2713644 Cache debug target for L2 Data RAM may not record correct data

# topic.topics[].topics[].topics[].label
2740664 PMU event 0x77 CRYPTO_SPEC does not always count when enabled

# topic.topics[].topics[].topics[].label
2751027 Load operation might abort unexpectedly when accessing poisoned data

# topic.topics[].topics[].topics[].label
2803663 Speculative dirty bit hardware update might happen for store operation

# topic.topics[].topics[].topics[].label
2833401 Direct access to internal memory might not be reliable

# topic.topics[].topics[].topics[].label
2841875 An uncontainable error might deadlock the cluster

# topic.topics[].topics[].topics[].label
2853709 Error record registers indicate incorrect feature support in configurations without cache protection

# topic.topics[].topics[].topics[].label
2861633 Some PMU events are incorrectly masked to trace unit

# topic.topics[].topics[].topics[].label
2871911 LDG or MTE checked load/store might fail to detect poisoned data

# topic.topics[].topics[].topics[].label
2872870 CE or DE errors from L1 data cache access might not be recorded in the RAS records

# topic.topics[].topics[].topics[].label
2879977 Unmodified cache line might be written back to memory

# topic.topics[].topics[].topics[].label
2940628 Store data might be lost when a correctable error is detected in the L1 data cache

# topic.topics[].topics[].topics[].label
2969138 Unmodified page table cache lines might be written back to memory

# topic.topics[].topics[].topics[].label
3067972 AMU does not count STALL_BACKEND_MEM correctly

# topic.topics[].topics[].topics[].label
3094433 The core might lose register accesses or interrupts in low-power state

# topic.topics[].topics[].topics[].label
3103429 STREX might raise both Synchronous and Asynchronous abort for external abort

# topic.topics[].topics[].topics[].label
3145557 Some PMU events for Operation speculatively executed do not count correctly

# topic.topics[].topics[].topics[].label
3185964 A watchpoint event might not be generated for a tag-checked SVE non-fault or first-fault load instruction

# topic.topics[].topics[].topics[].label
3186696 The virtual address is not sign extended in EDWAR

# topic.topics[].topics[].topics[].label
3311443 External registers PMCEID2 and PMCEID3 are not implemented

# topic.topics[].topics[].topics[].label
3326745 Power transition from EMU_OFF to OFF might not complete

# topic.topics[].topics[].topics[].label
3445783 Some PMU events do not count correctly

# topic.topics[].topics[].topics[].label
3531773 TRBE might record the wrong status/syndrome information in the TRBSR_EL1 register

# topic.topics[].topics[].topics[].label
3542363 Load/Store instruction might get unexpected translation fault

# topic.topics[].topics[].topics[].label
3600964 A Non-cacheable store exclusive instruction receiving an NDErr or DErr response might update memory and raise synchronous abort

# topic.topics[].topics[].topics[].label
3604547 Some PMU events do not count correctly

# topic.topics[].topics[].topics[].label
3650470 Core in a dual core complex might complete power transition to OFF while a CTI trigger is in progress

# topic.topics[].topics[].topics[].label
3660280 CPU might incorrectly wake up from WFE state due to a virtual event stream when in FULL_RET power mode

# topic.topics[].topics[].topics[].label
3680961 Core might not execute some instructions in debug state after a reset catch debug event is generated

# topic.topics[].topics[].topics[].label
3685405 The wrong shareability might be selected for instruction fetches when HCR_EL2.FWB == 1 while accessing a Non-shareable memory region

# topic.topics[].topics[].topics[].label
3701090 IRG produces biased tag generation when GCR_EL1.RRND == 1

# topic.topics[].topics[].topics[].label
3705320 Interrupt signals generated by cores might be deasserted when in retention

# topic.topics[].topics[].topics[].label
3729900 Performance might drop for core 1 in a 2-core complex configuration

# topic.topics[].topics[].topics[].label
3738908 Consecutive CTI trigger events from the same ELA output might not be sent to the CTI

# topic.topics[].topics[].topics[].label
3762369 Incorrect ESR_EL1.ISS.EX or ESR_EL2.ISS.EX for Software Step Exceptions

# topic.topics[].topics[].topics[].label
3777128 CTI trigger events from a core in Standby state might not be sent correctly

# topic.topics[].topics[].topics[].label
3777132 External debug request while transitioning to emulated off might cause core to deadlock

# topic.topics[].topics[].topics[].label
3817217 Affinity ID info in Complex_RAS.ERRDEVAFF register is not correct in single-core complex configuration

# topic.topics[].topics[].topics[].label
3952854 An ECC error detected during a core powerdown might result in data corruption or deadlock

# topic.topics[].topics[].topics[].label
4042385 An ECC error might generate data corruption

# topic.topics[].topics[].topics[].label
4109497 ETE and ELA timestamps are not accurate

# topic.topics[].topics[].topics[].label
4185709 L1 Instruction cache tag RAM ECC Error might be reported multiple times

# topic.topics[].topics[].topics[].label
4198903 Core might not stall when trace unit stalling is enabled

# topic.topics[].topics[].topics[].label
4454362 TRBE might not record the TRBSR_EL1.WRAP bit correctly

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.