# title
Arm Cortex-A720 MP151 Software Developer Errata Notice

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Arm® Cortex®-A720 MP151 Software Developer Errata Notice

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4689339 The CNT_CYCLES event can have a significant increment error due to WFE/WFI

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4410496 The TRBE forces wrong padding data during ETE draining, which corrupts the ETE trace

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4315981 TRBE trigger mode does not respect TRBSR_EL1.TRG

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3711910 DSB ST instructions might not properly order younger loads

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3699561 Read of ICH_VMCR_EL2.VBPR1 might return incorrect data based on SCR_EL3.NS

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3645544 TBRE might write to memory for which it does not have write permissions

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3456091 MSR PSTATE.SSBS to 0 is not fully self-synchronizing

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2940794 Load crossing a 64B boundary might cause data corruption

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2926083 Enabling the Statistical Profiling Extension might lead to deadlock

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2844092 Values of FAR_ELx and ESR_ELx on an Instruction Abort might not be consistent with the instruction that generated the fault

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2792132 Crossing 4K loads might cause data corruption or deadlock

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2729604 An FP/SIMD Data-Processing instruction reading a General-Purpose register might cause the core to deadlock

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2724969 Read requests generated by the L2 data prefetcher might generate MPAM information using PARTID_I/PMG_I rather than PARTID_D/PMG_D

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2641656 Data Cache Clean operations by VA might cause the PE to deadlock

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2621464 Values of FAR_ELx and ESR_ELx on an Instruction Abort might not be consistent with the instruction that generated the fault

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2615075 CPU might violate restrictions on instructions fetches when all stages of translation are disabled

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2561043 Speculatively executing 4KB-crossing loads might lead to data corruption

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2463007 Reads of CNTVCTSS_EL0 might be performed speculatively

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2689241 Concurrent modification and execution of instructions in the same PE might not succeed

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4694127 SPE PMSEVFR_EL1 allows writes to RAZ/WI bits [15:13]

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4554298 Continuous ELA trigger activity might prevent core power down

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4491856 DC GVA instructions might update allocation tags twice

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4106547 ETE and ELA timestamps are not accurate for core

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3963933 Core might deadlock after leaving WARM_RST, DBG_RECOV or OFF_EMU power modes

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3703762 Some PMU events might have incorrect values

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3655256 ESR.IESB can have an incorrect value on SError

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3655076 PSTATE.{PAN,UAO} synchronization might not be honored while MSR PSTATE is speculative

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3637708 EDSCR.STATUS not updated on Halting Step when a Load-Exclusive instruction generates a synchronous exception

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3072740 SVE first faulting load crossing a 64B boundary might silently corrupt data in case of double external abort

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2940640 Use of Tagged pages when Tag Checking is disabled might cause significant performance degradation

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2821794 Checked load crossing 4K boundary might fail to report a tag check fault into TFSR_ELx

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2802390 Hardware update of the Access flag or Dirty bit might cause corruption of Allocation Tags for translation table descriptors

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2752414 CFP RCTX might fail to invalidate the specified ASID and VMID

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2742807 PMU counters might fail to freeze on overflow

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2740679 Some PMU events might have incorrect values

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2738461 AMU Event 0x0011, Core frequency cycles might increment incorrectly when the core is in WFE state

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2711875 Information in some Statistical Profiling Extension packets might be incorrect

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2700891 An MTE checked store might report a speculative SError in case of poisoned tags

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2694688 Read accesses to memory-mapped RAS registers might fail to return the expected value

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2693172 The PE might not respond to APB accesses to some registers in OFF_EMU state

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2684560 Interrupts might be taken following a Context Synchronization Event when MDSR_EL1.INTdis or EDSCR.INTdis are set

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2659723 A continuous flow of snoops and other instructions might prevent a store from becoming visible in finite time

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2648296 ESR_ELx for a Breakpoint exception might be incorrect if breakpoints are concurrently disabled through APB

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2631723 RAMINDEX operations accessing the L1 Data cache might fail to return the correct result

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2625934 UNDEFINED exceptions due to EDSCR.SDD might be prioritized over EL2 traps caused by HCR_EL2.TIDCP

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2623527 Setting CPUECTLR2_EL1[11] might cause the PE to deadlock

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2621369 Some PMU events might have incorrect values

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2568091 Cross-4KB Neon/SVE load instructions might observe poison that is present on another cache line

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2561142 Checked First-Fault Neon/SVE load instructions might take a synchronous exception instead of updating FFR upon DBE on L1 Tag and external abort from the system

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2477399 Incorrect transition to Software-Step Active state after OSLAR_EL1.OSLK write followed by ERET

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2464850 Information in some Statistical Profiling Extension packets might be incorrect

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2458921 Checked stores in precise mode might fail to report tag check fails

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2455243 Crossing 4KB load might report incorrect FFR index

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2430467 Software-step with no instruction step after debug-exit from EL0 with a bad mode in DSPSR

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2303132 Instruction sampling bias exists in SPE implementation

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.