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Arm Cortex-A520AE Core Software Developer Errata Notice

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Arm® Cortex®-A520AE Core Software Developer Errata Notice

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3435249 Unmodified MTE tags might be written back to memory

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3559262 Power transition to FULL_RET is denied if FUNC_RET is also enabled

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3672346 CPU non-secure physical timer event interrupt might be triggered incorrectly

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3674306 Store operations might modify data twice

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3711577 CAS/CASP atomic instruction might get data corruption under certain condition

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3802424 Complex power transition might deadlock when a Utility bus or Debug APB access is sent to a core

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3919721 Power transition might deadlock on Utility Bus or APB access

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4568616 Faulting load might disclose data from previous load through side channel

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3326983 A watchpoint event might not be generated for a tag-checked SVE non-fault or first-fault load instruction

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3414408 The virtual address is not sign extended in EDWAR

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3435248 The core might lose register accesses or interrupts in low-power state

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3470103 Some PMU events do not count correctly

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3545700 Power transition from EMU_OFF to OFF might not complete

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3562078 Load/Store instruction might get unexpected translation fault

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3563909 TRBE might record the wrong status/syndrome information in the TRBSR_EL1 register

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3608624 A Non-cacheable store exclusive instruction receiving an NDErr or DErr response might update memory and raise synchronous abort

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3627235 Some PMU events for Operation speculatively executed do not count correctly

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3627236 External registers PMCEID2 and PMCEID3 are not implemented

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3650478 Core in a dual core complex might complete power transition to OFF while a CTI trigger is in progress

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3658235 Some PMU events do not count correctly

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3660306 CPU might incorrectly wake up from WFE state due to a virtual event stream when in FULL_RET power mode

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3675352 Core might not execute some instructions in debug state after a reset catch debug event is generated

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3676732 Interrupt signals generated by cores might be deasserted when in retention

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3685406 The wrong shareability might be selected for instruction fetches when HCR_EL2.FWB == 1 while accessing a Non-shareable memory region

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3715577 IRG produces biased tag generation when GCR_EL1.RRND == 1

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3727550 Performance might drop for core 1 in a 2-core complex configuration

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3738915 Consecutive CTI trigger events from the same ELA output might not be sent to the CTI

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3786005 CTI trigger events from a core in Standby state might not be sent correctly

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3786500 External debug request while transitioning to emulated off might cause core to deadlock

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3791686 Incorrect ESR_EL1.ISS.EX or ESR_EL2.ISS.EX for Software Step Exceptions

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3817614 Affinity ID info in Complex_RAS.ERRDEVAFF register is not correct in single-core complex configuration

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3990231 An ECC error detected during a core powerdown might result in deadlock

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4109510 ETE and ELA timestamps are not accurate for core or complex

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4112455 An ECC error might generate data corruption

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4279500 L1 Instruction cache tag RAM ECC Error might be reported multiple times

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4302440 Core might not stall when trace unit stalling is enabled

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4454363 TRBE might not record the TRBSR_EL1.WRAP bit correctly

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.