# title
Arm Cortex-M85 Software Developer Errata Notice

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Arm® Cortex®-M85 Software Developer Errata Notice

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2467111 Conditional LCTP may use out of date flag values for bypass or update of LTPSIZE

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2355499 Under limited circumstances, write-through store operations do not update the data cache correctly

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2286936 Aliased branch prediction in an IT block near an exception entry or BLXNS may result in incorrect execution

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2615656 Under certain conditions, an unaligned MVE load can return incorrect data for the lower word in its second tick if an older store is writing the same word

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3776601 AIRCR.SYSRESETREQ might be cleared before reset is asserted

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3190818 Under limited circumstances, LDM to normal non-cacheable AXI location can not complete

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3175626 AXI hang due to dependency between read data channel and write response channel

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2627033 An LDR following a flushed LDM targeting the same Non-cacheable line can return corrupted data

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2425308 When an MVE store encounters a fault, in some cases the FAR is not updated to the address of the beat that reports the fault

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2449355 A word-crossing store which gets an ignored BusFault for one of its words can cause a hang when dual-issued with a younger Device load

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2485388 An ongoing DSB does not wait for the automatic invalidation of the data cache to complete before retiring

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2371188 A flag writing external coprocessor instruction may cause incorrect bypass from younger conditional instructions

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2296335 DWT Watchpoints might not work reliably on Data address and Data value comparator matches

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2266165 An ignored bus fault can cause an operation to not make forward progress

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2247184 Automatic EWIC register save/restore sequence in some rare cases disables EWIC capability of recognizing wakeup events

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2257706 Under limited circumstances, store operations do not update the data cache correctly

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2312674 Under limited circumstances, PLDs to the same cache line address as pending line-fills cause duplicate cache allocation and thus data corruption

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2338043 The fields IDC, IXC, UFC, OFC and IOC in the FPSCR might be corrupted after the execution of double precision floating point multiply and accumulate instruction

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2295129 From an unprivileged debugger, cache maintenance and ERRDEVID registers are not accessible while ERRIIDR is accessible

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2309351 Incorrect values may be read from FP registers and VPR

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2722045 Under certain conditions, a load or store crossing into an MPU UNDEFINED region can report an unaligned UsageFault instead of the expected MemManage Fault

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2958637 Certain PMU EVENTBUS events not driven correctly

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2288773 A VLDRD executing in big-endian mode returns incorrect data if the load reads a word from device memory that is fully predicated when the other word isn't fully predicated

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2288808 Under limited circumstances, loads do not properly hazard other cache updates which cause a duplicate entry to be placed in the data cache causing data corruption

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2315530 IESB derived fault hang during entry

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2705514 Under limited circumstances, an LDM following a flushed LDM from Non-cacheable region can result in deadlock

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2434209 Certain stall cases can cause an unaligned MVE load to incorrectly zero some of its return data or fail to report a fault

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3078268 Incorrect multi-copy atomicity ordering between Non-cacheable loads with forwarded store data

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2682779 After deactivating the instruction cache, self-modified code might not be executed correctly

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2677972 CTITRIGIN not connected to DWT_CMPMATCH for ETM = 0 configuration

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2601889 Under limited circumstances, an ECC error on data cache RAMs can lead to data corruption

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2674410 An AXI load reading some portion of a word that an older store is writing might fail to report a BusFault in certain situations

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2374351 Trace fails to update PC on Imprecise bus fault under IESB fault escalation

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2374615 FP exception flags in the FPSCR might be set incorrectly after FP context creation following a security state change

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2371473 The execution priority might be incorrect for a cycle when an IRQ's priority is updated in its handler

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2365142 Direct cache access to Instruction cache data RAM cannot read half of the RAM locations

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2434651 An aligned doubleword MVE load reading the ITCM with one word predicated out might read data corrupted by an ECC error for the non-predicated word

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2434207 An MVE tick that encounters faults in both beats may report the FAR address incorrectly if the fault types for each beat are different

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2388605 A cacheable load which misses the data cache due to a correctable tag ECC error can return stale data if the cacheline it is reading is dirty

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2397109 An Instruction might be incorrectly sent to Embedded Trace Macrocell as partially completed instruction

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2445488 ETM incorrectly reports there are also additional serious exceptions when reporting entry into a serious exception

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2446484 Simultaneous ECC errors on a store tag lookup and a load data read in the data cache can cause the ECC error for the load to not get corrected

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2444277 Store data value for certain MVE stores is incorrect to DWT for data value matching

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2452728 Before RAM power is up and completes cache auto invalidation sequence, i.e. D$ is accessible, a cacheable store data might not be observed by a load to the same address after D$ is accessible

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2459389 Executing VSCCLRM with an invalid ICI value may raise INVSTATE UsageFault

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2451384 CHAIN PMU event unconnected to PMU EVENTBUS

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2439477 A Secure read of ICSR_NS.VECTPENDING might return the Secure value

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2456913 Under limited circumstances, an LDM to a normal non-cacheable location followed by store to the same location might prevent the core from transitioning to lower power mode

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2432946 ETM reports wrong address on tail-chain during sleep on exit

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2746551 Store address to DWT incorrect for certain VSTR operations

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2666664 Under limited conditions, an unaligned MVE load reading the TCMs may return corrupted data if it encounters a transient BusFault on its TCM read

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2651727 Unprivileged debug transactions to the STIR and EVENTSPR registers can pend interrupts

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2666660 An unusual combination of events can cause the core to hang instead of lock up on SOE entry

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2490920 A malformed tail-predicated loop at the start of a Secure function may use the value of LTPSIZE without masking

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2467154 S-AHB read bursts might terminate prematurely in case TCM Error is encountered by a speculatively prefetched read which immediately follows a read that encounters correctable ECC error

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2631240 Unexpected writes to DEBRs can potentially stop the outstanding linefills from completion

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2589246 An incorrect fault address is reported for an unprivileged aligned doubleword store to the STIR and RFSR registers when CCR.USERSETMPEND is set

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2355269 A DWORD-sized store access to ITM_CIDR2 and ITM_CIDR3 can fault incorrectly on the access to the ITM_CIDR3 when the store is not privileged

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2374269 Unprivileged debugger access allowed to read or write the DPDLPSTATE register

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2374006 Undefined 16bit opcodes could raise a NOCP UsageFault instead of an UNDEFINSTR UsageFault

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3030982 Store data value for certain aligned vector stores incorrect to DWT for data value matching

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2253502 An interstating LDM may restart using an incorrect base address

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2319196 DWT_PCSR can present next non-committed instruction when no instruction retirement occurs in the core

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2272772 Debug read to FPSCR may return wrong default value

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2266957 Incorrect execution priority may be applied for a short duration in rare cases after the start of an IRQ return

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2297046 RTL incorrectly halts as it incorrectly computes vector catch on lockup entry

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2276413 Debug writes to privleged only bits of current state using DCRSR may not occur if UDE is enabled

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2282154 Under limited circumstances, a load to a normal non-cacheable location might not be properly ordered by a barrier instruction

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2279775 An UNDEFINSTR fault could be prioritized over an INVSTATE fault for some invalid ICI values

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2283939 TCM requests that receive both a TGU fault and have forwarded data do not properly report a TGU fault

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2323280 Word crossing store accesses that access the last word of the PAHB memory region might cause data corruption or incorrect fault behavior

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2321988 LSERR v/s NOCP Fault prioritization during PushStack

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2312664 Under limited circumstances, LDRD or VLDR instructions that access both device and non-device memory can deadlock the memory system

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2335473 A load or store multiple might cause an incorrect ICI value to be stacked in the RETPSR

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2311453 Flaw in memory system power down may result in data corruption

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2902253 ITM can generate synchronization and timestamp packets when NIDEN=0

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2757159 Under limited circumstances, store operations do not update the data cache correctly

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2988396 DWT data value packets can be generated while the match packet from same access overflows

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4035919 DWT_FUNCTION.MATCHED not asserted on comparator match when debug event does not have sufficient priority to preempt

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3319763 ACTLR_S bit[11] can not disable No Write-Allocate mode

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3492897 CTI event may be lost when CTI is enabled

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2640876 Load data value for certain unaligned vector loads incorrect to DWT for data value matching

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2265059 A store with memory attributes that do not match a younger LDM to the same address may cause a hang

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2242544 Data corruption may be observed if there are consecutive reads to different Wakeup Event Mask registers

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2287723 The vector register file may not be cleared when tail chaining from a secure to non-secure exception

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2614056 Under limited conditions, a doubleword-aligned doubleword ITCM load can read data corrupted by an ECC error

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4008397 Some PMU events might undercount

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3876894 PMU events LL_CACHE_RD and LL_CACHE_MISS_RD cannot be counted

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2593278 Under limited conditions, an imprecise abort may not be reported when a tag RAM ECC error is detected and data loss has occurred

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2705117 L1D_CACHE_REFILL and L1D_CACHE_MISS_RD PMU events might be inaccurate

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2253509 A debug monitor step may cause an incorrect ICI value to be stacked in the RETPSR

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4506875 MSCR.CPWRDN fails to be set when Instruction Cache automatic invalidation sequence is in progress

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4518246 DWT can incorrectly emit overflow and suppress data address or value trace packets for unaligned doubleword MVE store

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4429357 S-AHB Transactions are not being ignored during WARM_RESET state

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.