# title
Arm Cortex-A715 Core MP148 Software Developer Errata Notice

# topic.label
Arm® Cortex®-A715 Core MP148 Software Developer Errata Notice

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2357487 A stream of stashes, cache maintenance operations, MTE-checked stores or atomics might cause the core to deadlock or lose coherency

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4410674 The TRBE forces wrong padding data during ETE draining, which corrupts the ETE trace

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3711916 DSB ST instructions might not properly order younger loads

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3699560 Read of ICH_VMCR_EL2.VBPR1 might return incorrect data based on SCR_EL3.NS

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3647005 TBRE might write to memory for which it does not have write permissions

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3456084 MSR PSTATE.SSBS to 0 is not fully self-synchronizing

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2804830 Writes of a 64B-aligned, 64B granule of memory might cause data corruption

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2645198 Values of FAR_ELx and ESR_ELx on an Instruction Abort might not be consistent with the instruction that generated the fault

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2615073 CPU might violate restrictions on instructions fetches when all stages of translation are disabled

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2561034 Speculatively executing 4KB-crossing loads might lead to data corruption

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2429384 Executing uncacheable loads might lead to deadlock

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2420947 Executing a store and store release on the same cacheline might lead to corruption

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2418468 Crossing 4K loads might cause ordering violation or silent corruption in MTE asymmetric mode

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2413290 Enabling the Statistical Profiling Extension might lead to deadlock

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2409570 Store-Release instructions might not be observed in the correct order

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2376701 LDFF/LDNF can generate a corrupted First Fault Register

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2344187 Slow MRS instruction can get corrupted data

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2331818 Store might never complete a coherency operation, leading to deadlock

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2330952 A continuous stream of incoming DVM syncs may cause TRBE to prevent the core from forward progressing

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2317812 Sequential consistency might not be respected with a non cacheable Store-Release

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2302347 Write-After-Write ordering might be violated in presence of STLR

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2292761 Executing code in a context with multiple VAs mapped to the same PA might lead to an opcode corruption

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2287512 Entry into the Full Retention power mode might cause corruption on Itag, Idata, and TLB RAMs

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2285473 A LDR executed between two Non-Cacheable LDRs to the same 64B boundary might fail to apply ordered-before semantics to said instructions

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2285536 TRBE might generate corrupt trace data and/or fail to complete all pending accesses following a DSB or DVM Sync

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2284544 Exclusive store might deadlock under very specific timing conditions

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2275754 Speculatively executed store behind constantly mis-predicted branch might prevent forward progress of synchronization primitives in other PEs

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2268070 Data Cache Clean operations by VA to the Point of Coherency, Point of Persistence, or Point of Deep Persistence might cause the PE to deadlock

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2248167 ESR_ELx and FAR_ELx might report incorrect information on Instruction Abort when hardware breakpoints are enabled

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2239006 The PE might generate memory accesses using invalidated mappings after completion of a DVM SYNC operation.

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2238661 In MTE precise mode, Load with writeback can cause the PE to deadlock

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2180026 Reset value of MDCR_EL2.HPMN does not reflect the number of implemented PMU counters

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2728106 Concurrent modification and execution of instructions in the same PE might not succeed

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4491864 DC GVA instructions might update allocation tags twice

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3963939 Core might deadlock after leaving WARM_RST, DBG_RECOV or OFF_EMU power modes

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3655329 ESR.IESB can have an incorrect value on SError

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3655081 PSTATE.{PAN,UAO} synchronization might not be honored while MSR PSTATE is speculative

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3638030 EDSCR.STATUS not updated on Halting Step when a Load-Exclusive instruction generates a synchronous exception

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3072736 SVE first faulting load crossing a 64B boundary might silently corrupt data in case of double external abort

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2850830 Checked load crossing 4K boundary might fail to report a tag check fault into TFSR_ELx

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2808741 Hardware update of the Access flag or Dirty bit might cause corruption of Allocation Tags for translation table descriptors

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2752541 CFP RCTX might fail to invalidate the specified ASID and VMID

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2738462 AMU Event 0x0011, Core frequency cycles might increment incorrectly when the core is in WFE state

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2731260 Some PMU events might have incorrect values

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2712353 Information in some Statistical Profiling Extension packets might be incorrect

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2709709 Interrupts might be taken following a Context Synchronization Event when MDSR_EL1.INTdis or EDSCR.INTdis are set

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2701325 The PE might not respond to APB accesses to some registers in OFF_EMU

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2661229 ESR_ELx for a Breakpoint exception might be incorrect if breakpoints are concurrently disabled through APB

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2631695 Incorrect transition to Software-Step Active state after OSLAR_EL1.OSLK write followed by ERET

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2631722 RAMINDEX operations accessing the L1 Data cache might fail to return the correct result

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2625935 UNDEFINED exceptions due to EDSCR.SDD might be prioritized over EL2 traps caused by HCR_EL2.TIDCP

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2574284 Software-step with no instruction step after debug-exit from EL0 with a bad mode in DSPSR

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2460643 Checked stores in precise mode might fail to report tag check fails

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2455253 Crossing 4KB load might report incorrect FFR index

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2428886 ERXSTATUS_EL1.OF might incorrectly be set in case of multiple errors

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2426380 Cacheable load might return corrupted data upon single-bit error in L1 data cache tag RAM

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2424427 Uncacheable 32-bytes loads might fail to report poison information

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2422640 A continuous flow of snoops and atomics might prevent a store from becoming visible in finite time

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2411188 ESR_ELx.ISV might be incorrect when software-stepping an MSR DAIF instruction

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2389413 Some PMU events might have incorrect values

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2387304 Checked crossing 64B boundary load might fail to report a tag check fault

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2385318 PMCFGR.EX and PMCR_EL0.X should be 0

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2372608 Double bit error in L2 Tag RAM might lead to deadlock or protocol violation

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2354488 Information in some Statistical Profiling Extension packets might be incorrect

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2328270 Trace Buffer Extension might fail to complete all pending accesses following a Data Synchronization Barrier or Distributed Virtual Memory Sync

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2318005 SPE Issue Latency counter might be incorrect on sampled operations generating an exception

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2312234 Set/Way CMO instructions might not affect a cache line stored in the L1 victim cache

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2310079 PMBSR_EL1 might report a Data Abort instead of a Buffer Management Event when PMBPTR_EL1 reaches PMBLIMITR_EL1

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2305209 Executing an ESB might fail to clear a masked Virtual SError Interrupt

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2301922 Some PMU events might have incorrect values

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2293949 Instruction sampling bias exists in SPE implementation

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2276160 PMU event DTLB_WALK might incorrectly count some instructions in case of EPD/E0PD translation fault

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2268885 PE might generate spurious Branch Target exceptions when dynamically changing the GP bit in page tables

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2262629 Checked store in precise mode might deadlock in case of external abort

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2259398 Software-step not done after exit from Debug state with an illegal value in DSPSR

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2252693 Table walks generated by the Trace Buffer Extension might use MPAM information of the current Exception level rather than the TBE owning translation regime

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2247884 A continuous stream of stores might prevent an older store from becoming visible in finite time

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2246816 Disabling MPMM through Utility Bus can cause a deadlock

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2238988 A continuous stream of stores might prevent forward progress of a coherency operation

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2238597 A MTE checked store might report a speculative SError in case of poisoned tags

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2238671 SVE PRFM instructions fail to prefetch at the expected address

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2227533 APB accesses to unallocated addresses might generate an PSLVERR response

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2220769 Read or write from Secure EL1 for ICV_BPR1_EL1 register might not work

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2189618 ELR_ELx might contain an incorrect value on exceptions taken from PC 0xFFFF_0000_0000_0000

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2187565 A double-bit ECC error on the L2 TQ RAM for a store might fail to mark the data as poisoned

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2182762 Direct RAM Access read on IData RAM might return corrupted data

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2180579 Load/Store instructions might fail to report double-bit ECC errors, and/or External aborts, and/or cause loss of poison information

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2171772 A double-bit ECC error or poison on tags on a First-fault load might result in a Synchronous Tag Check Fault instead of a Synchronous External abort

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2168152 Persistent errors on SVE First-fault instructions might result in deadlock under specific conditions

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2160316 Trace data might miss some packets or contain incorrect packets when enabled through the APB interface

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.