# title
Arm Cortex-A510 Core (MP111) Software Developer Errata Notice

# topic.label
Arm® Cortex-A510 Core (MP111) Software Developer Errata Notice

# topic.topics[].topics[].topics[].label
1921103 TLBI completion might not be guaranteed by DSB

# topic.topics[].topics[].topics[].label
1927171 Mismatched memory attributes might cause deadlock

# topic.topics[].topics[].topics[].label
1943861 Acquire/release semantics violated on store atomic instructions

# topic.topics[].topics[].topics[].label
1946214 Heavy L2 memory traffic may lead to data corruption and deadlock

# topic.topics[].topics[].topics[].label
1970520 Secure Physical Address Cache Invalidate all DVM operation does not invalidate Non-Secure lines in L1 I-Cache

# topic.topics[].topics[].topics[].label
1996706 A deadlock might occur during or after WFI or WFE

# topic.topics[].topics[].topics[].label
2007174 Heavy store traffic might lead to a DSB not completing on the same core or another core

# topic.topics[].topics[].topics[].label
2039708 Non-cacheable stores, maintenance, or speculation restriction instructions might cause a deadlock

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2069773 Forwarding snoops might cause a deadlock

# topic.topics[].topics[].topics[].label
2184257 Normal execution can result in data corruption

# topic.topics[].topics[].topics[].label
2217821 Heavy I-cache invalidation or TLB invalidation traffic from other PEs can cause a deadlock

# topic.topics[].topics[].topics[].label
2454944 Unmodified cache line might be written back to memory

# topic.topics[].topics[].topics[].label
1965350 Coherency might be lost on a cache line

# topic.topics[].topics[].topics[].label
1975996 Non-L1-allocating stores might cause data corruption

# topic.topics[].topics[].topics[].label
1902691 Trace Buffer Extension can cause trace corruption or deadlock

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1910738 Use of tagged memory might cause deadlock, data corruption or incorrect reporting

# topic.topics[].topics[].topics[].label
1922240 SnpPreferUnique* might lead to a loss of coherency

# topic.topics[].topics[].topics[].label
1937669 Tag Checked store might not be correctly ordered by DMB

# topic.topics[].topics[].topics[].label
1942494 A cacheable load of SIMD&FP or SVE registers might return incorrect data

# topic.topics[].topics[].topics[].label
1943339 Cacheable far atomics might result in loss of coherency

# topic.topics[].topics[].topics[].label
1952872 A cacheable load might return incorrect data

# topic.topics[].topics[].topics[].label
1955641 Core in FULL_RET might cause data corruption

# topic.topics[].topics[].topics[].label
1956116 Missing trace for debug entry due to watchpoint hit

# topic.topics[].topics[].topics[].label
1961781 Watchpoints on SVE first-fault and non-fault loads might cause an incorrect value to be loaded and/or an incorrect MTE check results

# topic.topics[].topics[].topics[].label
1962857 Set/way maintenance of L2 cache might cause data corruption

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1966377 Incorrect instructions might be executed

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1975068 Cacheable Non-shareable mappings might lead to CHI protocol violations

# topic.topics[].topics[].topics[].label
1977575 Coherency might be lost on a cache line shortly after a core powers up

# topic.topics[].topics[].topics[].label
1981843 A store exclusive to shareable memory other than Normal Inner Write-Back, Outer Write-Back Cacheable might cause a hang

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2008766 RAS errors during core power down might cause a deadlock

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2014530 Debug accesses while leaving OFF_EMU power mode might lead to a system deadlock

# topic.topics[].topics[].topics[].label
2015106 Memory mapped accesses to MPMM registers have the wrong offset

# topic.topics[].topics[].topics[].label
2022138 Core in FULL_RET might not have clock gated

# topic.topics[].topics[].topics[].label
2027318 SnpPreferUnique might lead to a loss of coherency

# topic.topics[].topics[].topics[].label
2028010 A PRF{U}M instruction might hang

# topic.topics[].topics[].topics[].label
2038114 EDSCR.STATUS might be incorrect when single stepping a Load-Exclusive instruction

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2038923 A change to TRBLIMITR_EL1.E might result in trace buffer corruption

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2039165 Debug accesses while leaving OFF_EMU power mode might lead to a system deadlock

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2041661 Entry into the Full Retention power mode might cause incorrect execution of a TLB maintenance instruction

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2041909 Load-Exclusive/Store-Exclusive loop might not make forward progress

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2042739 A store or Load-Exclusive might cause data corruption

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2044951 Entry into FUNC_RET power mode can cause data metastability

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2051678 A hardware update of the dirty bit might not be correctly ordered with respect to later instructions

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2061513 TRBE might cause a speculative hardware update of the dirty bit outside the trace buffer range

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2064142 A system register write might not take effect after the trace buffer is disabled

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2069954 A hardware update of the dirty bit might occur speculatively if PSTATE.PAN is used

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2077057 Software stepping ERETAA or ERETAB might corrupt SPSR_ELx

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2082334 ERR2STATUS.SERR might be incorrect

# topic.topics[].topics[].topics[].label
2135898 DSPSR_EL0.BTYPE might be incorrect on Debug state entry

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2141267 LD1R using SP as base register incorrectly requests MTE Tag Checked

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2148497 A trace unit trigger might result in inconsistent register state of the Trace Buffer Extension

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2156527 Mapping memory as Tagged when Allocation Tag storage is not provided might lead to CHI protocol violations or Tag corruption

# topic.topics[].topics[].topics[].label
2169012 SnpPreferUnique* might lead to a loss of coherency

# topic.topics[].topics[].topics[].label
2172148 Snp*UniqueFwd might cause a deadlock or data corruption

# topic.topics[].topics[].topics[].label
2218134 Single-bit error in branch predictor memory can cause instruction fetch stream corruption

# topic.topics[].topics[].topics[].label
2218950 Aliased loads and stores might cause an ordering violation

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2250311 Asynchronous exceptions while MPMM is active might corrupt processor state

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2256538 Hardware breakpoints might not be taken on 32-bit T32 instructions

# topic.topics[].topics[].topics[].label
2288014 Data corruption might occur in rare circumstances

# topic.topics[].topics[].topics[].label
2314929 TLB Invalidation prevents core OFF_EMU to OFF transition

# topic.topics[].topics[].topics[].label
2347730 Executing a WFI/WFE with VPU powerdown enabled might result in a deadlock

# topic.topics[].topics[].topics[].label
2358024 EDSCR.INTdis might not mask Non-secure interrupts

# topic.topics[].topics[].topics[].label
2371937 Cacheable far atomics might generate data corruption

# topic.topics[].topics[].topics[].label
2420992 Incorrect instructions might be executed

# topic.topics[].topics[].topics[].label
2658417 BFMMLA or VMMLA instructions might produce incorrect result

# topic.topics[].topics[].topics[].label
2666669 Data corruption might occur during core powerdown

# topic.topics[].topics[].topics[].label
2675636 An asynchronous MTE check might not observe correct memory ordering

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2684597 A core might deadlock during powerdown if TRBE is enabled

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2724177 Deferred error might become uncontainable

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2971420 Data corruption or deadlock might happen if TRBE is enabled

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3057514 Deferred error might become uncontainable when BROADCASTMTE is set

# topic.topics[].topics[].topics[].label
3117295 A speculatively executed unprivileged load might leak data from a privileged via side channel

# topic.topics[].topics[].topics[].label
3672349 CPU non-secure physical timer event interrupt might be triggered incorrectly

# topic.topics[].topics[].topics[].label
3704847 CAS/CASP atomic instruction might get data corruption under certain conditions

# topic.topics[].topics[].topics[].label
4568615 Faulting load might disclose data from previous load through side channel

# topic.topics[].topics[].topics[].label
4659130 Core power transition from OFF to ON might lead to deadlock

# topic.topics[].topics[].topics[].label
1976290 A Tag Checked load might forward incorrect data

# topic.topics[].topics[].topics[].label
2002389 Asynchronous exceptions after ECC errors might cause unpredictable behavior

# topic.topics[].topics[].topics[].label
2080326 A longer TLBI sequence might cause a deadlock

# topic.topics[].topics[].topics[].label
2277097 CMOs to non-shareable locations might deadlock the cluster

# topic.topics[].topics[].topics[].label
2441009 Completion of affected memory accesses might not be guaranteed by completion of a TLBI

# topic.topics[].topics[].topics[].label
1898949 Execution of an atomic instruction may fail to make forward progress

# topic.topics[].topics[].topics[].label
1904476 Reads of GMID_EL1 might trap to incorrect exception level when MTE is disabled

# topic.topics[].topics[].topics[].label
1905896 Error responses to MakeReadUnique transactions might result in data corruption

# topic.topics[].topics[].topics[].label
1911617 Tag Check Fault reporting might be incorrect when ECC error occurs

# topic.topics[].topics[].topics[].label
1915215 Software stepping ERETAA or ERETAB might set SPSR.ELx.SS to incorrect value

# topic.topics[].topics[].topics[].label
1921977 Error response to load-exclusive might cause loss of synchronization or deadlock

# topic.topics[].topics[].topics[].label
1924991 Accesses to TRCQCTLR are RAZ/WI instead of UNDEFINED

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1925280 A single-bit error in the L2DB RAMs might be reported incorrectly as a corrected error

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1929084 Direct access to L1 data cache MTE data RAMs does not function

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1933869 Writes to DBGWCR<n>_EL1/DBGWVR<n>_EL1 might cause speculative reads of device memory

# topic.topics[].topics[].topics[].label
1934328 Multiple errors detected on the same cycle might lead to an incorrect value of ERR2STATUS and ERR2MISC0

# topic.topics[].topics[].topics[].label
1946400 Error reporting disabled does not mask error responses on memory accesses

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1951345 PMU_HOVFS event exported when EL2 trace disabled

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1951423 An ECC error during core power down might cause another error to occur after power up

# topic.topics[].topics[].topics[].label
1951568 PMU event counts might be inaccurate

# topic.topics[].topics[].topics[].label
1954191 L2 cache debug operations might hang and block a power off request

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1954658 ERR2STATUS.CE might be incorrect

# topic.topics[].topics[].topics[].label
1955046 External events are not observed after Warm reset

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1955072 Mapping memory as Tagged when Allocation Tag storage is not provided might lead to CHI protocol violations

# topic.topics[].topics[].topics[].label
1956538 Execution of ESB instruction in debug state might cause unpredictable behavior

# topic.topics[].topics[].topics[].label
1959615 Exceptions in debug state might allow execution of subsequent instruction in EDITR

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1964078 VMID tracing incorrectly allowed or disallowed based on TRFCR_EL2.CX

# topic.topics[].topics[].topics[].label
1965154 PMU snapshot records incorrect Context ID when PMU inactive

# topic.topics[].topics[].topics[].label
1966395 A continuous stream of stores might prevent forward progress of a coherency operation

# topic.topics[].topics[].topics[].label
1974927 SIMD, FP, and SVE cacheable loads or MTE-checked stores might hang on accessing a poisoned cache line

# topic.topics[].topics[].topics[].label
1975007 WFE trap might take effect when a wake up event is pending

# topic.topics[].topics[].topics[].label
1976399 PrefetchTgt transactions are generated when PrefetchTgt is disabled

# topic.topics[].topics[].topics[].label
1977191 Trigger received immediately out of warm reset might cause deadlock

# topic.topics[].topics[].topics[].label
1980125 A change of ASID without context synchronization might cause memory ordering issues

# topic.topics[].topics[].topics[].label
1980599 An ECC error in the L1 data cache might not be detected

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1981723 A continuous stream of DVM operations from another PE might block core powerdown

# topic.topics[].topics[].topics[].label
1982956 SIMD and floating point loads to non-gatherable device memory might over-read

# topic.topics[].topics[].topics[].label
1986930 Corruption might occur on MTE allocation tags

# topic.topics[].topics[].topics[].label
1987125 ERR2MISC0.OFR and ERR2MISC0.OFO might not be set on counter overflow

# topic.topics[].topics[].topics[].label
1987184 DBG_RECOV or WARM_RST power modes might lead to deadlock or data corruption

# topic.topics[].topics[].topics[].label
1990749 Errors or poison in the L2 data RAM might lead to deadlock and/or data corruption

# topic.topics[].topics[].topics[].label
1991004 Uncontainable error injection via ERR2PFGCTL might occur at the wrong time

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1991342 Traps of System registers in Debug state might cause unexpected exceptions

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1996476 A Tag Checked SVE non-fault or first-fault load might hang if an External abort occurs

# topic.topics[].topics[].topics[].label
1996886 ELA connected to warm reset instead of cold reset

# topic.topics[].topics[].topics[].label
1997011 Asynchronous Tag Check fail not synchronized based on SCTLR_ELx.ITFSB for exceptions in Debug state

# topic.topics[].topics[].topics[].label
1998835 Double-bit errors in the duplicate L1 data cache tag RAMs might lead to loss of coherency or deadlock

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1999032 Non-Data Errors on memory accesses not attributable to a core might not be reported

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2000000 Interrupt might not be taken in finite time

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2006188 L2 cache debug operations might hang when no L2 cache is present

# topic.topics[].topics[].topics[].label
2012183 Double-bit errors in the duplicate L1 data cache tag RAMs might lead to deadlock on a snoop

# topic.topics[].topics[].topics[].label
2015240 Clearing a pending OS Unlock Catch debug event might cause unpredictable behavior

# topic.topics[].topics[].topics[].label
2016064 A continuous stream of memory requests from one CPU in the complex might block another

# topic.topics[].topics[].topics[].label
2017921 Exception or DCPS3 instruction in debug state might block execution of instruction from EDITR

# topic.topics[].topics[].topics[].label
2025809 A double-bit error on the L1 data cache MTE tag RAMs might result in a missed or incorrect error record in ERR1STATUS

# topic.topics[].topics[].topics[].label
2033473 A hardware update of the dirty bit might occur speculatively

# topic.topics[].topics[].topics[].label
2035302 CONTEXTIDR_EL2 breakpoint matching is enabled at EL3

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2036369 MPAM3_EL3.TRAPLOWER reset on Cold reset

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2048342 A load or store instruction might hang when encountering multiple uncorrectable or deferred errors

# topic.topics[].topics[].topics[].label
2052205 ERR2STATUS.SERR might be incorrect after an NDErr response is received

# topic.topics[].topics[].topics[].label
2052374 PMU event ST_RETIRED might be inaccurate for Store-Exclusive instructions

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2053387 Instructions in Debug state after a watchpoint debug event might not be executed

# topic.topics[].topics[].topics[].label
2054370 Execution of instructions in Debug state after a watchpoint debug event might incorrectly set EDSCR.ERR and corrupt PSTATE

# topic.topics[].topics[].topics[].label
2056307 A Tag Checked store exclusive might hang if an external abort occurs

# topic.topics[].topics[].topics[].label
2059297 PSTATE.TCO might be unchanged for debug entry due to a watchpoint debug event

# topic.topics[].topics[].topics[].label
2071968 Incorrect context ID might be associated with trace data

# topic.topics[].topics[].topics[].label
2077160 Incorrect ordering after change in cacheability

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2077274 Extra A-sync packet might get written to Trace Buffer in Trace prohibited region

# topic.topics[].topics[].topics[].label
2085871 Shareability aliases might result in incorrect Tag Check Faults

# topic.topics[].topics[].topics[].label
2088637 A watchpointed SVE load might update the FFR register incorrectly

# topic.topics[].topics[].topics[].label
2092740 Debug state exit after execution of a DRPS instruction might lead to deadlock

# topic.topics[].topics[].topics[].label
2096738 Double-bit errors in the duplicate L1 data cache tag RAMs might lead to deadlock

# topic.topics[].topics[].topics[].label
2112025 Instructions might be missed for tracing purposes before Debug state entry due to a watchpoint hit

# topic.topics[].topics[].topics[].label
2120833 DISR_EL1 access in Debug state might be incorrect

# topic.topics[].topics[].topics[].label
2133769 PMU event 0x000C PC_WRITE_RETIRED might be inaccurate for ERET instructions

# topic.topics[].topics[].topics[].label
2135690 PMU events based on STALL_FRONTEND might be inaccurate

# topic.topics[].topics[].topics[].label
2141037 OFF_EMU to OFF power mode transition might result in a deadlock

# topic.topics[].topics[].topics[].label
2146058 PMU events counts might be inaccurate

# topic.topics[].topics[].topics[].label
2161448 PMU_HOVFS event not always exported when self-hosted trace disabled

# topic.topics[].topics[].topics[].label
2164605 A watchpoint hit while disabling Halting debug might cause an incorrect debug exception to be taken

# topic.topics[].topics[].topics[].label
2175229 A single ECC error on the L2 data RAMs might be double-counted

# topic.topics[].topics[].topics[].label
2181318 A PE trace unit trigger might not be reflected in TRBSR_EL1 after a TSB

# topic.topics[].topics[].topics[].label
2187223 In Halting debug state, the core might take an illegal execution exception when it should not

# topic.topics[].topics[].topics[].label
2189260 An MMU fault might not be correctly reflected in the Trace Buffer Extension TRBSR_EL1 register

# topic.topics[].topics[].topics[].label
2189707 Clean MTE tag writeback might occur after a store to the cache line

# topic.topics[].topics[].topics[].label
2212805 An ECC error while in the active-not-pending state might clear PSTATE.SS

# topic.topics[].topics[].topics[].label
2217109 RAS error reporting might be incorrect on simultaneous errors

# topic.topics[].topics[].topics[].label
2220074 ETM will indicate that a T32 CC-failed ISB has caused a Context Synchronization Event when it has not

# topic.topics[].topics[].topics[].label
2226937 IMP_CDBGDR0_EL3 read data might be incorrect

# topic.topics[].topics[].topics[].label
2230537 Load following SVE predicated load/store might cause ordering violation

# topic.topics[].topics[].topics[].label
2236402 Asynchronous exception or debug event might be taken before an exception catch debug event that was generated by an exception entry

# topic.topics[].topics[].topics[].label
2241478 The L1D_CACHE_REFILL and L1D_CACHE_LMISS_RD PMU events might over-count

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2265919 Top byte of DLR_EL0 might be incorrect when entering AArch64 halting Debug state

# topic.topics[].topics[].topics[].label
2266023 Vector stores might not use a faster forwarding path

# topic.topics[].topics[].topics[].label
2271084 DTR flags not cleared on external debugger access while leaving Debug state

# topic.topics[].topics[].topics[].label
2272274 Core might execute two instructions on Halting Step debug event

# topic.topics[].topics[].topics[].label
2287488 Core might not execute instruction on Halting Step debug event

# topic.topics[].topics[].topics[].label
2289541 PMU counter overflow can cause spurious PMU_OVFS and PMU_HOVFS events

# topic.topics[].topics[].topics[].label
2289878 Core might step two instructions at once

# topic.topics[].topics[].topics[].label
2291784 PSTATE.IL might be cleared on ERET to Software Stepping

# topic.topics[].topics[].topics[].label
2293834 The core might report that a load-exclusive instruction has not been stepped when it should

# topic.topics[].topics[].topics[].label
2300878 Software stepping ESB might set SPSR.ELx.SS to incorrect value

# topic.topics[].topics[].topics[].label
2303522 Synchronous tag checking on a store exclusive might cause a deadlock if double bit/fatal error seen in L1-Duplicate RAM

# topic.topics[].topics[].topics[].label
2316094 MTE checking might not be reliable

# topic.topics[].topics[].topics[].label
2321712 DLR_EL0[1] is ignored when performing debug exit to A32

# topic.topics[].topics[].topics[].label
2324165 Processor state might be corrupted if EDSCR.INTdis is set while asynchronous interrupt is in flight

# topic.topics[].topics[].topics[].label
2331844 Software stepping ERET might set PSTATE or SPSR to incorrect value

# topic.topics[].topics[].topics[].label
2335678 BFMMLA/VMMLA result might be corrupted when forwarding source operand from vector load

# topic.topics[].topics[].topics[].label
2341012 Physical SError interrupts while software stepping a load or store instruction might cause two instructions to be stepped

# topic.topics[].topics[].topics[].label
2342004 TLB Parity Check cannot be disabled

# topic.topics[].topics[].topics[].label
2342918 PrefetchTgt transactions are generated when PrefetchTgt is disabled

# topic.topics[].topics[].topics[].label
2360589 Exception catch might not be taken on ERET from EL3 to any Non-secure EL

# topic.topics[].topics[].topics[].label
2371559 ESR_ELx might be incorrect after trapped vector instruction in Debug state

# topic.topics[].topics[].topics[].label
2385664 Core might not execute any instruction when performing Halting Step

# topic.topics[].topics[].topics[].label
2393935 ESR_ELx.EX might be incorrect when stepping a load exclusive

# topic.topics[].topics[].topics[].label
2396657 ESR_ELx.EX might be incorrect due to asynchronous exception when software stepping

# topic.topics[].topics[].topics[].label
2423961 PMU_OVFS event is not generated on PMCCNTR_EL0 overflow

# topic.topics[].topics[].topics[].label
2429106 Exception Catch debug event might not be taken

# topic.topics[].topics[].topics[].label
2429770 PC_WRITE_SPEC event does not count correctly

# topic.topics[].topics[].topics[].label
2478655 L2D_CACHE_WB event might over-count

# topic.topics[].topics[].topics[].label
2601282 ELADISABLE does not disable APB access to the complex ELA

# topic.topics[].topics[].topics[].label
2618004 LDST_SPEC event might under-count

# topic.topics[].topics[].topics[].label
2636015 BUS_ACCESS and BUS_ACCESS_WR PMU events are not reliable

# topic.topics[].topics[].topics[].label
2679270 External aborts reporting can not be disabled

# topic.topics[].topics[].topics[].label
2688792 PMU event L3D_CACHE_LMISS_RD might be inaccurate

# topic.topics[].topics[].topics[].label
2690487 Some architectural PMU events are not always available to trace unit

# topic.topics[].topics[].topics[].label
2710402 Read value of IMP_CPUCFR_EL1 might be incorrect

# topic.topics[].topics[].topics[].label
2713359 ERR2STATUS.UET field might be incorrect

# topic.topics[].topics[].topics[].label
2718749 Cache debug target for L2 Data RAM may not record correct data

# topic.topics[].topics[].topics[].label
2834345 Direct access to internal memory might not be reliable

# topic.topics[].topics[].topics[].label
2856823 Speculative dirty bit hardware update might happen for store operation

# topic.topics[].topics[].topics[].label
2867016 An uncontainable error might deadlock the cluster

# topic.topics[].topics[].topics[].label
2867018 Error record registers indicate incorrect feature support in configurations without cache protection

# topic.topics[].topics[].topics[].label
2878694 LDG or MTE checked load/store might fail to detect poisoned data

# topic.topics[].topics[].topics[].label
2879976 Unmodified cache line might be written back to memory

# topic.topics[].topics[].topics[].label
2971621 Unmodified page table cache lines might be written back to memory

# topic.topics[].topics[].topics[].label
2976328 Store data might be lost when a correctable error is detected in the L1 data cache

# topic.topics[].topics[].topics[].label
3129886 STALL_BACKEND_MEM event is not counted correctly

# topic.topics[].topics[].topics[].label
3186698 The virtual address is not sign extended in EDWAR

# topic.topics[].topics[].topics[].label
3199345 Some PMU events for Operation speculatively executed do not count correctly

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3311453 External registers PMCEID2 and PMCEID3 are not implemented

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3600903 TRBE might record the wrong status/syndrome information in the TRBSR_EL1 register

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3660309 CPU might incorrectly wake up from WFE state due to a virtual event stream when in FULL_RET power mode

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3674595 Core might not execute some instructions in debug state after a reset catch debug event is generated

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3685398 The wrong shareability might be selected for instruction fetches when HCR_EL2.FWB == 1 while accessing a Non-shareable memory region

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3701094 IRG produces biased tag generation when GCR_EL1.RRND == 1

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3718988 Interrupt signals generated by cores might be deasserted when in retention

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3738906 Consecutive CTI trigger events from the same ELA output might not be sent to the CTI

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3762368 Incorrect ESR_EL1.ISS.EX or ESR_EL2.ISS.EX for Software Step Exceptions

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3777130 CTI trigger events from a core in Standby state might not be sent correctly

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3777133 External debug request while transitioning to emulated off might cause core to deadlock

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4185711 L1 Instruction cache tag RAM ECC Error might be reported multiple times

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4198904 Core might not stall when trace unit stalling is enabled

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4450369 TRBE might not record the TRBSR_EL1.WRAP bit correctly

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.