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Arm CoreLink MMU-700 System Memory Management Unit Software Developer Errata Notice

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Arm® CoreLink™ MMU-700 System Memory Management Unit Software Developer Errata Notice

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1917448 HTTU operations cannot be used when stage 1 and stage 2 translation is enabled

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1781134 MPAM partition hard limit sometimes exceeded

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1832597 Secure transactions result in incorrect C_BAD_STE event under certain conditions

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1848465 Termination of stalls might sometimes not occur

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1854758 Register reads to the TBU do not complete under certain conditions

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1932231 Incorrect read data for some registers

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1941946 Some invalidation operations might not succeed

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2105620 TLB allocation inefficient in certain conditions

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2133013 Stage 1 DVM invalidation operations of translations using TTB1 might not succeed

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2216408 Invalidated transactions might sometimes complete after SYNC completion

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2239241 MPAM CMAX register write uses incorrect bits from the write data

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2268618 TLBI (R)IPAS2* and CMD_TLBI(_S)_S2_IPA invalidation of nested translations currently in progress might not succeed

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2428613 TBU or ATS connection process can sometimes cause deadlock

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2650791 MPAM monitor values incorrect if configuration changed while enabled

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2812531 Walk cache updates sent incorrectly after invalidation

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3610531 TCU hazarding causes incorrect translation when PTEs are updated

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3777127 Under invalidation in TBU possible when using contiguous page table entries

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2214515 Global entries are not always invalidated as expected

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2808817 A device that can issue FIXED bursts can bypass hypervisor Force Write-Back controls to read old memory contents

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4014544 Possible under-invalidation in TBU TLB when using STE CONT

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1768143 Non-zero value of SSID generated in PRI response when SSV is 0

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1781603 Event queue not overflowing when filled and fault not reported

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1784630 Incorrect IPA in fault syndrome reported for HTTU enabled nested translations

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1871067 C_BAD_STE not asserted under certain conditions

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1877245 RAS error can result in RAS registers read data being corrupted

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1879539 Incorrect fault data sometimes reported

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1912550 Incorrect shareability for Cache Maintenance Operations (CMOs)

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2093540 TCU Performance Monitoring Event indicating Config Cache Read inaccurate

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2120193 C_BAD_STREAMID not asserted in certain conditions

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2288256 Configuration and translation structures might be accessed by prefetch transactions while SMMU(_S)_CR0.SMMUEN=0 and SMMU(_S)_CR0ACK.SMMUEN=0

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2621157 Multiple Events reported to Event queue for a single transaction

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2626480 PMU event 0x2 (TLB Miss) triggers incorrectly in TCU

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2674701 Read of TCU_MSMON_CAPT_EVNT register returns data instead of zero

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2803259 Incorrect merging of S1 Allocation hints

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2842669 Incorrect MPAM_MSMON_IDR value for NO_HW_OFLW_INTR bit [30]

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2900780 Stream table base address not properly aligned when log2size is configured greater than stream ID size

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2945011 Address size fault raised when some RES0 page table descriptor bits have non-zero values

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3243556 NSIPA field in the Event record incorrect in certain conditions

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3422699 CD.ASID value might affect caching of EL3 and some EL2 contexts

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3673196 A power down sequence which does not result in a reset of the SMMU might leave stale data in the cache on power up

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3898590 F_ADDR_SIZE is not triggered for S1L1 blocks with 64Kb granules with certain CD.IPS values

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.