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Arm Cortex-M55 AT633 and Cortex-M55 with FPU AT634 Software Developer Errata Notice

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Arm® Cortex®-M55 AT633 and Cortex®-M55 with FPU AT634 Software Developer Errata Notice

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1735179 Incorrect result written to the scalar register file for an MVE VMOV (general-purpose register to vector lane) instruction

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1707936 Unprivileged DAP accesses can modify the debug monitor exception enable

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1717323 Non-cacheable loads might not observe previous Non-cacheable stores

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1720713 Pending interrupts might get lost or corrupted when entering sleep using EWIC automatic sequence

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1721673 Deadlock due to Write-through Write-allocate store to location that always gets a bus error

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1729416 Automatic cache invalidation does not occur on Warm reset

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1732413 A VLLDM might restore a lazy context when flushed by an asynchronous halt request

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2184678 Unprivileged debugger access to some SCB registers incorrectly modifies register state

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2217780 A partially completed VLLDM might leave Secure floating-point, or vector data unprotected

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2233762 An interrupted vector instruction with implicit LE might cause the ETM to generate an Address packet with the wrong PC

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2277273 Cache maintenance registers and ERRDEVID are not accessible from an unprivileged debugger

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2428419 Automatic EWIC drain will not function if the processor is powered down during sleep when the secure extension is not configured

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3776408 AIRCR.SYSRESETREQ might be cleared before reset is asserted

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1698164 Processor might not step correctly after a branch which changes security state

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1709730 ETM might trace some interrupted instructions incorrectly

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1733006 ITM stall might not guarantee delivery of hardware trace packets

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1736567 An INVPC exception on FunctionReturn can target the wrong Security state

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1740040 The LR can be corrupted when the last instruction of a loop is overlapped and interrupted

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1745058 Processor might step two consecutive exception entries when debug halt stepping

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1746023 PMU event counting and processor halting might not work as expected

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1784253 Invalid DWT trace on MVE load or store with predication

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1784383 Execution priority might be incorrect for one cycle for a Debug Monitor event after AIRCR, ITNS, IPR or SHPRn is changed

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1794743 When the DWT stalls the processor an instruction or data might be traced as part of the following instruction

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1803238 Some PMU events might be inaccurate

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1810002 An instruction or exception which causes lockup might not enter debug state when expected

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1849620 Trace might be incorrect when Unprivileged debug is enabled

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1858750 A branch that is taken after an interstating branch that has not been taken might incorrectly fetch as if it is in Non-secure state

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1871826 The DWT might incorrectly expose the address of a BXNS

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1960594 Performance Monitor Unit is not disabled on Warm reset

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2019023 The DWT might incorrectly expose the IPSR of a Secure exception when the ITM stall is enabled and Secure non-invasive debug is prohibited

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2080562 A Secure unprivileged debugger write to DSCSR.CDS may be ignored

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2085795 The DWT might incorrectly generate a match on the address or data of a memory transaction which is not performed

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2117423 A WFx Instruction may not be traced by the DWT when ITM stall is enabled

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2129008 A Secure read of ICSR_NS.VECTPENDING might return the Secure value

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2132823 TPIU does not generate frame synchronization packets when TPIU_PSCR is programmed with a value greater than 16

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2134265 A faulting vector load/store instruction might not be traced by the DWT when ITM stall is enabled

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2161015 When tracing an exception the ETM may incorrectly indicate a serious fault is pending

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2173589 SBIST AHB interconnect can forward the incorrect value for HSEL

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2176014 A hardware breakpoint might be ignored after a Secure function call with unaligned SG

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2219778 Conditional instruction tracing might not work due to an interrupted VSTM, when ETM is configured to trace condition codes for data instructions only

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2226595 The DWT might generate a Data trace PC value packet with the incorrect PC, when ITM stall is enabled

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2252094 PMU cycle counter and PMU event counter incorrectly stop counting when there is an overflow

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2267938 The DWT might not trace an instruction when ITM stall is enabled

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2285085 DWT Performance Profiling Counters might sometimes have an incorrect value

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2295637 DWT_FUNCTION.MATCHED of the DWT Comparator gets cleared on a Speculative read that gets cancelled

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2312624 Trace reconstruction might be incorrect, due to invalid exception return address on a Lockup exception

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2397983 PMU event L1I_CACHE is incorrectly implemented in the instruction cache

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2454643 A VSTMDB which specifies unimplemented registers may write to unexpected memory locations

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2461408 Unprivileged debugger access to DPDLPSTATE register incorrectly modifies register state

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2567270 A BX using the LR where the t-bit (bit[0]) of the LR is not set, under certain circumstances, might not cause a INVSTATE fault

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2619476 TCM ECC errors for S-AHB accesses will not be reported in sleep state

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2653102 Unprivileged debug transactions to the STIR and EVENTSPR registers can pend interrupts

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2675831 After deactivating the instruction cache self-modified code might not be executed correctly

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2703268 L1D_CACHE_REFILL and L1D_CACHE_MISS_RD PMU events might be inaccurate

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2791503 ITM can generate Synchronization and timestamp packets when NIDEN=0

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3130083 Sequentially executing across a Non-Secure to Secure Non-secure Callable boundary can incorrectly prioritise the INVEP fault

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3863575 PMU events LL_CACHE_RD and LL_CACHE_MISS_RD cannot be counted

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4034034 DWT_FUNCTION.MATCHED not asserted on comparator match when debug event does not have sufficient priority to preempt

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4486602 MSCR.CPWRDN fails to be set when Instruction Cache automatic invalidation sequence is in progress

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.