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Arm Cortex-M23 Processor Device Generic User Guide

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Arm® Cortex®-M23 Processor Device Generic User Guide

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Cortex-M23 Devices Generic User Guide Introduction

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About the Cortex-M23 processor and core peripherals

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Processor modes and privilege levels for software execution

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The Cortex Microcontroller Software Interface Standard

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Additional memory access constraints for caches and shared memory

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Programming hints for the synchronization primitives

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ADC, ADD, RSB, SBC, and SUB restrictions

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Accessing the Cortex-M23 NVIC registers using CMSIS

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Hardware and software control of interrupts

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Application Interrupt and Reset Control Register

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System Handler Control and State Register

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Security Attribution and Memory Protection

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Security Attribution Unit Control Register

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Security Attribution Unit Region Number Register

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Security Attribution Unit Region Base Address Register

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Security Attribution Unit Region Limit Address Register

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MPU Memory Attribute Indirection Register 0 and MPU Memory Attribute Indirection Register 1

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FUSAEN I/O for debug and trace logic protection

# metadata.contentDescription
User Guide for software developers wanting to use Arm Cortex-M23 Devices. The processor is a highly deterministic low-end 32-bit MCU implementing the Armv8-M architecture.