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Arm RSE in Arm Neoverse CSS V3 Operational Guidance

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Arm® RSE in Arm® Neoverse® CSS V3 Operational Guidance

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DMA boot in CM life cycle state (Virgin mode) and RMA life cycle state

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DMA boot in CM lifecycle state, non-virgin modes

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BL1-1 setting of the TRAM key slot in KMU

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RSE software behavior control using OTP-provisioned values

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Running DFT tests on the RSE and its SoC

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First provisioning step: chip manufacturing

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Chip manufacturing provisioning — programming guidance

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Second provisioning step: device manufacturing

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Device return: transition to RMA lifecycle state

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Software access to system memory and peripherals

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Integrity checker usage by DMA during boot

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Integrity checker usage by software in runtime

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Integrity calculation using the integrity checker

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AES double operation (DFA countermeasure)

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TRAM reinitialization after memory retention

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Avoid polluting the data cache when copying large data

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Correcting ECC following partial writes to VM0 and VM1

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Correcting ECC following SEC ECC error in VM0 and VM1

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Handling of DED ECC error in VM0 and VM1

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Prevention of ECC errors caused by speculative cache prefetching

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Prefetching of data from VM0, VM1, and DTCM

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Handling of RSE cold reset initiated by SAM

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Handling of processor DCLS reported errors

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Handling of processor RAS reported errors

# metadata.contentDescription
This document gives an overview of the functionality of the Runtime Security Engine integrated into the Arm Neoverse CSS V3.