# title
Arm Architecture Registers for FAT A-profile architecture ASL1

# topic.label
Arm Architecture Registers for FAT A-profile architecture ASL1

# topic.topics[].topics[].label
ADFSR: Auxiliary Data Fault Status Register

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AIFSR: Auxiliary Instruction Fault Status Register

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AMAIR0: Auxiliary Memory Attribute Indirection Register 0

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AMAIR1: Auxiliary Memory Attribute Indirection Register 1

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AMCFGR: Activity Monitors Configuration Register

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AMCGCR: Activity Monitors Counter Group Configuration Register

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AMCNTENCLR0: Activity Monitors Count Enable Clear Register 0

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AMCNTENCLR1: Activity Monitors Count Enable Clear Register 1

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AMCNTENSET0: Activity Monitors Count Enable Set Register 0

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AMCNTENSET1: Activity Monitors Count Enable Set Register 1

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AMCR: Activity Monitors Control Register

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AMEVCNTR0<n>: Activity Monitors Event Counter Registers 0

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AMEVCNTR1<n>: Activity Monitors Event Counter Registers 1

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AMEVTYPER0<n>: Activity Monitors Event Type Registers 0

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AMEVTYPER1<n>: Activity Monitors Event Type Registers 1

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AMUSERENR: Activity Monitors User Enable Register

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APSR: Application Program Status Register

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CCSIDR2: Current Cache Size ID Register 2

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CNTHCTL: Counter-timer Hyp Control register

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CNTHPS_CTL: Counter-timer Secure Physical Timer Control Register (EL2)

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CNTHPS_CVAL: Counter-timer Secure Physical Timer CompareValue Register (EL2)

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CNTHPS_TVAL: Counter-timer Secure Physical Timer TimerValue Register (EL2)

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CNTHP_CTL: Counter-timer Hyp Physical Timer Control register

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CNTHP_CVAL: Counter-timer Hyp Physical CompareValue register

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CNTHP_TVAL: Counter-timer Hyp Physical Timer TimerValue register

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CNTHVS_CTL: Counter-timer Secure Virtual Timer Control Register (EL2)

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CNTHVS_CVAL: Counter-timer Secure Virtual Timer CompareValue Register (EL2)

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CNTHVS_TVAL: Counter-timer Secure Virtual Timer TimerValue Register (EL2)

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CNTHV_CTL: Counter-timer Virtual Timer Control register (EL2)

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CNTHV_CVAL: Counter-timer Virtual Timer CompareValue register (EL2)

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CNTHV_TVAL: Counter-timer Virtual Timer TimerValue register (EL2)

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CNTKCTL: Counter-timer Kernel Control register

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CNTPCT: Counter-timer Physical Count register

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CNTP_CTL: Counter-timer Physical Timer Control register

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CNTP_TVAL: Counter-timer Physical Timer TimerValue register

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CNTVCT: Counter-timer Virtual Count register

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CNTVOFF: Counter-timer Virtual Offset register

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CNTV_CTL: Counter-timer Virtual Timer Control register

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CNTV_CVAL: Counter-timer Virtual Timer CompareValue register

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CNTV_TVAL: Counter-timer Virtual Timer TimerValue register

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CPACR: Architectural Feature Access Control Register

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DBGBCR<n>: Debug Breakpoint Control Registers

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DBGBVR<n>: Debug Breakpoint Value Registers

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DBGBXVR<n>: Debug Breakpoint Extended Value Registers

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DBGCLAIMCLR: Debug CLAIM Tag Clear register

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DBGCLAIMSET: Debug CLAIM Tag Set register

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DBGDCCINT: DCC Interrupt Enable Register

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DBGDSCRext: Debug Status and Control Register, External View

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DBGDSCRint: Debug Status and Control Register, Internal View

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DBGDTRRXext: Debug OS Lock Data Transfer Register, Receive, External View

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DBGDTRRXint: Debug Data Transfer Register, Receive

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DBGDTRTXext: Debug OS Lock Data Transfer Register, Transmit

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DBGDTRTXint: Debug Data Transfer Register, Transmit

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DBGOSECCR: Debug OS Lock Exception Catch Control Register

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DBGWCR<n>: Debug Watchpoint Control Registers

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DBGWFAR: Debug Watchpoint Fault Address Register

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DBGWVR<n>: Debug Watchpoint Value Registers

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DISR: Deferred Interrupt Status Register

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DSPSR: Debug Saved Program Status Register

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DSPSR2: Debug Saved Process State Register 2

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ELR_hyp: Exception Link Register (Hyp mode)

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ERXADDR: Selected Error Record Address Register

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ERXADDR2: Selected Error Record Address Register 2

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ERXCTLR: Selected Error Record Control Register

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ERXCTLR2: Selected Error Record Control Register 2

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ERXFR: Selected Error Record Feature Register

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ERXFR2: Selected Error Record Feature Register 2

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ERXMISC0: Selected Error Record Miscellaneous Register 0

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ERXMISC1: Selected Error Record Miscellaneous Register 1

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ERXMISC2: Selected Error Record Miscellaneous Register 2

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ERXMISC3: Selected Error Record Miscellaneous Register 3

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ERXMISC4: Selected Error Record Miscellaneous Register 4

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ERXMISC5: Selected Error Record Miscellaneous Register 5

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ERXMISC6: Selected Error Record Miscellaneous Register 6

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ERXMISC7: Selected Error Record Miscellaneous Register 7

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ERXSTATUS: Selected Error Record Primary Status Register

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FPEXC: Floating-Point Exception Control register

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FPSCR: Floating-Point Status and Control Register

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FPSID: Floating-Point System ID register

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HACR: Hyp Auxiliary Configuration Register

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HACTLR2: Hyp Auxiliary Control Register 2

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HADFSR: Hyp Auxiliary Data Fault Status Register

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HAIFSR: Hyp Auxiliary Instruction Fault Status Register

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HAMAIR0: Hyp Auxiliary Memory Attribute Indirection Register 0

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HAMAIR1: Hyp Auxiliary Memory Attribute Indirection Register 1

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HCPTR: Hyp Architectural Feature Trap Register

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HIFAR: Hyp Instruction Fault Address Register

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HMAIR0: Hyp Memory Attribute Indirection Register 0

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HMAIR1: Hyp Memory Attribute Indirection Register 1

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HTRFCR: Hyp Trace Filter Control Register

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HTTBR: Hyp Translation Table Base Register

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ICC_AP0R<n>: Interrupt Controller Active Priorities Group 0 Registers

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ICC_AP1R<n>: Interrupt Controller Active Priorities Group 1 Registers

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ICC_ASGI1R: Interrupt Controller Alias Software Generated Interrupt Group 1 Register

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ICC_BPR0: Interrupt Controller Binary Point Register 0

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ICC_BPR1: Interrupt Controller Binary Point Register 1

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ICC_CTLR: Interrupt Controller Control Register

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ICC_DIR: Interrupt Controller Deactivate Interrupt Register

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ICC_EOIR0: Interrupt Controller End Of Interrupt Register 0

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ICC_EOIR1: Interrupt Controller End Of Interrupt Register 1

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ICC_HPPIR0: Interrupt Controller Highest Priority Pending Interrupt Register 0

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ICC_HPPIR1: Interrupt Controller Highest Priority Pending Interrupt Register 1

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ICC_HSRE: Interrupt Controller Hyp System Register Enable register

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ICC_IAR0: Interrupt Controller Interrupt Acknowledge Register 0

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ICC_IAR1: Interrupt Controller Interrupt Acknowledge Register 1

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ICC_IGRPEN0: Interrupt Controller Interrupt Group 0 Enable register

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ICC_IGRPEN1: Interrupt Controller Interrupt Group 1 Enable register

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ICC_MCTLR: Interrupt Controller Monitor Control Register

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ICC_MGRPEN1: Interrupt Controller Monitor Interrupt Group 1 Enable register

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ICC_MSRE: Interrupt Controller Monitor System Register Enable register

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ICC_PMR: Interrupt Controller Interrupt Priority Mask Register

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ICC_RPR: Interrupt Controller Running Priority Register

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ICC_SGI0R: Interrupt Controller Software Generated Interrupt Group 0 Register

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ICC_SGI1R: Interrupt Controller Software Generated Interrupt Group 1 Register

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ICC_SRE: Interrupt Controller System Register Enable register

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ICH_AP0R<n>: Interrupt Controller Hyp Active Priorities Group 0 Registers

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ICH_AP1R<n>: Interrupt Controller Hyp Active Priorities Group 1 Registers

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ICH_EISR: Interrupt Controller End of Interrupt Status Register

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ICH_ELRSR: Interrupt Controller Empty List Register Status Register

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ICH_HCR: Interrupt Controller Hyp Control Register

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ICH_LR<n>: Interrupt Controller List Registers

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ICH_LRC<n>: Interrupt Controller List Registers

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ICH_MISR: Interrupt Controller Maintenance Interrupt State Register

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ICH_VMCR: Interrupt Controller Virtual Machine Control Register

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ICH_VTR: Interrupt Controller VGIC Type Register

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ICV_AP0R<n>: Interrupt Controller Virtual Active Priorities Group 0 Registers

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ICV_AP1R<n>: Interrupt Controller Virtual Active Priorities Group 1 Registers

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ICV_BPR0: Interrupt Controller Virtual Binary Point Register 0

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ICV_BPR1: Interrupt Controller Virtual Binary Point Register 1

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ICV_CTLR: Interrupt Controller Virtual Control Register

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ICV_DIR: Interrupt Controller Deactivate Virtual Interrupt Register

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ICV_EOIR0: Interrupt Controller Virtual End Of Interrupt Register 0

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ICV_EOIR1: Interrupt Controller Virtual End Of Interrupt Register 1

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ICV_HPPIR0: Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0

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ICV_HPPIR1: Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1

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ICV_IAR0: Interrupt Controller Virtual Interrupt Acknowledge Register 0

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ICV_IAR1: Interrupt Controller Virtual Interrupt Acknowledge Register 1

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ICV_IGRPEN0: Interrupt Controller Virtual Interrupt Group 0 Enable register

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ICV_IGRPEN1: Interrupt Controller Virtual Interrupt Group 1 Enable register

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ICV_PMR: Interrupt Controller Virtual Interrupt Priority Mask Register

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ICV_RPR: Interrupt Controller Virtual Running Priority Register

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ID_ISAR0: Instruction Set Attribute Register 0

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ID_ISAR1: Instruction Set Attribute Register 1

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ID_ISAR2: Instruction Set Attribute Register 2

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ID_ISAR3: Instruction Set Attribute Register 3

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ID_ISAR4: Instruction Set Attribute Register 4

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ID_ISAR5: Instruction Set Attribute Register 5

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ID_ISAR6: Instruction Set Attribute Register 6

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ID_MMFR0: Memory Model Feature Register 0

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ID_MMFR1: Memory Model Feature Register 1

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ID_MMFR2: Memory Model Feature Register 2

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ID_MMFR3: Memory Model Feature Register 3

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ID_MMFR4: Memory Model Feature Register 4

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ID_MMFR5: Memory Model Feature Register 5

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IFAR: Instruction Fault Address Register

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JMCR: Jazelle Main Configuration Register

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MAIR0: Memory Attribute Indirection Register 0

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MAIR1: Memory Attribute Indirection Register 1

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MVBAR: Monitor Vector Base Address Register

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NSACR: Non-Secure Access Control Register

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PMCCFILTR: Performance Monitors Cycle Count Filter Register

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PMCCNTR: Performance Monitors Cycle Count Register

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PMCEID0: Performance Monitors Common Event Identification register 0

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PMCEID1: Performance Monitors Common Event Identification register 1

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PMCEID2: Performance Monitors Common Event Identification register 2

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PMCEID3: Performance Monitors Common Event Identification register 3

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PMCNTENCLR: Performance Monitors Count Enable Clear register

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PMCNTENSET: Performance Monitors Count Enable Set register

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PMCR: Performance Monitors Control Register

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PMEVCNTR<n>: Performance Monitors Event Count Registers

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PMEVTYPER<n>: Performance Monitors Event Type Registers

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PMINTENCLR: Performance Monitors Interrupt Enable Clear register

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PMINTENSET: Performance Monitors Interrupt Enable Set register

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PMMIR: Performance Monitors Machine Identification Register

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PMOVSR: Performance Monitors Overflow Flag Status Register

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PMOVSSET: Performance Monitors Overflow Flag Status Set register

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PMSELR: Performance Monitors Event Counter Selection Register

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PMSWINC: Performance Monitors Software Increment register

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PMUSERENR: Performance Monitors User Enable Register

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PMXEVCNTR: Performance Monitors Selected Event Count Register

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PMXEVTYPER: Performance Monitors Selected Event Type Register

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RVBAR: Reset Vector Base Address Register

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SPSR_abt: Saved Program Status Register (Abort mode)

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SPSR_fiq: Saved Program Status Register (FIQ mode)

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SPSR_hyp: Saved Program Status Register (Hyp mode)

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SPSR_irq: Saved Program Status Register (IRQ mode)

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SPSR_mon: Saved Program Status Register (Monitor mode)

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SPSR_svc: Saved Program Status Register (Supervisor mode)

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SPSR_und: Saved Program Status Register (Undefined mode)

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TPIDRPRW: PL1 Software Thread ID Register

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TPIDRURO: PL0 Read-Only Software Thread ID Register

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TPIDRURW: PL0 Read/Write Software Thread ID Register

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TTBCR: Translation Table Base Control Register

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TTBCR2: Translation Table Base Control Register 2

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TTBR0: Translation Table Base Register 0

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TTBR1: Translation Table Base Register 1

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VDFSR: Virtual SError Exception Syndrome Register

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VDISR: Virtual Deferred Interrupt Status Register

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VPIDR: Virtualization Processor ID Register

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VTTBR: Virtualization Translation Table Base Register

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ACTLRMASK_EL1: Auxiliary Control Masking Register (EL1)

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ACTLRMASK_EL2: Auxiliary Control Masking Register (EL2)

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ACTLR_EL1: Auxiliary Control Register (EL1)

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ACTLR_EL2: Auxiliary Control Register (EL2)

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ACTLR_EL3: Auxiliary Control Register (EL3)

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AFGDTP<n>_EL1: Auxillary Fine Grained Dynamic Traps, Privileged (EL1)

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AFGDTP<n>_EL2: Auxillary Fine Grained Dynamic Traps, Privileged (EL2)

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AFGDTP<n>_EL3: Auxillary Fine Grained Dynamic Traps, Privileged (EL3)

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AFGDTU<n>_EL1: Auxillary Fine Grained Dynamic Traps, Unprivileged (EL1)

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AFGDTU<n>_EL2: Auxillary Fine Grained Dynamic Traps, Unprivileged (EL2)

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AFSR0_EL1: Auxiliary Fault Status Register 0 (EL1)

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AFSR0_EL2: Auxiliary Fault Status Register 0 (EL2)

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AFSR0_EL3: Auxiliary Fault Status Register 0 (EL3)

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AFSR1_EL1: Auxiliary Fault Status Register 1 (EL1)

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AFSR1_EL2: Auxiliary Fault Status Register 1 (EL2)

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AFSR1_EL3: Auxiliary Fault Status Register 1 (EL3)

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AMAIR2_EL1: Extended Auxiliary Memory Attribute Indirection Register (EL1)

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AMAIR2_EL2: Extended Auxiliary Memory Attribute Indirection Register (EL2)

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AMAIR2_EL3: Extended Auxiliary Memory Attribute Indirection Register (EL3)

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AMAIR_EL1: Auxiliary Memory Attribute Indirection Register (EL1)

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AMAIR_EL2: Auxiliary Memory Attribute Indirection Register (EL2)

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AMAIR_EL3: Auxiliary Memory Attribute Indirection Register (EL3)

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AMCG1IDR_EL0: Activity Monitors Counter Group 1 Identification Register

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AMCGCR_EL0: Activity Monitors Counter Group Configuration Register

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AMCNTENCLR0_EL0: Activity Monitors Count Enable Clear Register 0

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AMCNTENCLR1_EL0: Activity Monitors Count Enable Clear Register 1

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AMCNTENSET0_EL0: Activity Monitors Count Enable Set Register 0

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AMCNTENSET1_EL0: Activity Monitors Count Enable Set Register 1

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AMCR_EL0: Activity Monitors Control Register

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AMEVCNTR0<n>_EL0: Activity Monitors Event Counter Registers 0

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AMEVCNTR1<n>_EL0: Activity Monitors Event Counter Registers 1

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AMEVCNTVOFF0<n>_EL2: Activity Monitors Event Counter Virtual Offset Registers 0

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AMEVCNTVOFF1<n>_EL2: Activity Monitors Event Counter Virtual Offset Registers 1

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AMEVTYPER0<n>_EL0: Activity Monitors Event Type Registers 0

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AMEVTYPER1<n>_EL0: Activity Monitors Event Type Registers 1

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AMUSERENR_EL0: Activity Monitors User Enable Register

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APDAKeyHi_EL1: Pointer Authentication Key A for Data (bits[127:64])

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APDAKeyLo_EL1: Pointer Authentication Key A for Data (bits[63:0])

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APDBKeyHi_EL1: Pointer Authentication Key B for Data (bits[127:64])

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APDBKeyLo_EL1: Pointer Authentication Key B for Data (bits[63:0])

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APGAKeyHi_EL1: Pointer Authentication Key A for Code (bits[127:64])

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APGAKeyLo_EL1: Pointer Authentication Key A for Code (bits[63:0])

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APIAKeyHi_EL1: Pointer Authentication Key A for Instruction (bits[127:64])

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APIAKeyLo_EL1: Pointer Authentication Key A for Instruction (bits[63:0])

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APIBKeyHi_EL1: Pointer Authentication Key B for Instruction (bits[127:64])

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APIBKeyLo_EL1: Pointer Authentication Key B for Instruction (bits[63:0])

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BRBCR_EL1: Branch Record Buffer Control Register (EL1)

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BRBCR_EL2: Branch Record Buffer Control Register (EL2)

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BRBFCR_EL1: Branch Record Buffer Function Control Register

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BRBIDR0_EL1: Branch Record Buffer ID0 Register

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BRBINF<n>_EL1: Branch Record Buffer Information Register <n>

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BRBINFINJ_EL1: Branch Record Buffer Information Injection Register

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BRBSRC<n>_EL1: Branch Record Buffer Source Address Register <n>

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BRBSRCINJ_EL1: Branch Record Buffer Source Address Injection Register

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BRBTGT<n>_EL1: Branch Record Buffer Target Address Register <n>

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BRBTGTINJ_EL1: Branch Record Buffer Target Address Injection Register

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BRBTS_EL1: Branch Record Buffer Timestamp Register

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CCSIDR2_EL1: Current Cache Size ID Register 2

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CCSIDR_EL1: Current Cache Size ID Register

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CNTHPS_CTL_EL2: Counter-timer Secure Physical Timer Control Register (EL2)

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CNTHPS_CVAL_EL2: Counter-timer Secure Physical Timer CompareValue Register (EL2)

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CNTHPS_TVAL_EL2: Counter-timer Secure Physical Timer TimerValue Register (EL2)

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CNTHP_CTL_EL2: Counter-timer Hypervisor Physical Timer Control Register

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CNTHP_CVAL_EL2: Counter-timer Physical Timer CompareValue Register (EL2)

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CNTHP_TVAL_EL2: Counter-timer Physical Timer TimerValue Register (EL2)

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CNTHVS_CTL_EL2: Counter-timer Secure Virtual Timer Control Register (EL2)

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CNTHVS_CVAL_EL2: Counter-timer Secure Virtual Timer CompareValue Register (EL2)

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CNTHVS_TVAL_EL2: Counter-timer Secure Virtual Timer TimerValue Register (EL2)

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CNTHV_CTL_EL2: Counter-timer Virtual Timer Control Register (EL2)

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CNTHV_CVAL_EL2: Counter-timer Virtual Timer CompareValue Register (EL2)

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CNTHV_TVAL_EL2: Counter-timer Virtual Timer TimerValue Register (EL2)

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CNTPS_CTL_EL1: Counter-timer Physical Secure Timer Control Register

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CNTPS_TVAL_EL1: Counter-timer Physical Secure Timer TimerValue Register

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CNTP_CTL_EL0: Counter-timer Physical Timer Control Register

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CNTVCT_EL0: Counter-timer Virtual Count Register

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CNTV_CTL_EL0: Counter-timer Virtual Timer Control Register

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CONTEXTIDR_EL1: Context ID Register (EL1)

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CONTEXTIDR_EL2: Context ID Register (EL2)

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CPACRMASK_EL1: Architectural Feature Access Control Masking Register

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CPACR_EL1: Architectural Feature Access Control Register

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CPTRMASK_EL2: Architectural Feature Trap Masking Register

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CPTR_EL2: Architectural Feature Trap Register (EL2)

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CPTR_EL3: Architectural Feature Trap Register (EL3)

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CSSELR_EL1: Cache Size Selection Register

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DACR32_EL2: Domain Access Control Register

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DBGBVR<n>_EL1: Debug Breakpoint Value Registers

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DBGCLAIMCLR_EL1: Debug CLAIM Tag Clear Register

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DBGCLAIMSET_EL1: Debug CLAIM Tag Set Register

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DBGDTRRX_EL0: Debug Data Transfer Register, Receive

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DBGDTRTX_EL0: Debug Data Transfer Register, Transmit

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DBGDTR_EL0: Debug Data Transfer Register, half-duplex

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DBGPRCR_EL1: Debug Power Control Register

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DBGVCR32_EL2: Debug Vector Catch Register

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DBGWVR<n>_EL1: Debug Watchpoint Value Registers

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DISR_EL1: Deferred Interrupt Status Register

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DPOCR_EL0: Debug Permissions Overlays Control Register

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DPOTBR0_EL1: Data Permission Overlay Table Register 0 (EL1)

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DPOTBR0_EL2: Data Permission Overlay Table Register 0 (EL2)

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DPOTBR0_EL3: Data Permission Overlay Table Register 0 (EL3)

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DPOTBR1_EL1: Data Permission Overlay Table Register 1 (EL1)

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DPOTBR1_EL2: Data Permission Overlay Table Register 1 (EL2)

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DSPSR_EL0: Debug Saved Program Status Register

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ERRSELR_EL1: Error Record Select Register

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ERXADDR_EL1: Selected Error Record Address Register

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ERXCTLR_EL1: Selected Error Record Control Register

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ERXFR_EL1: Selected Error Record Feature Register

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ERXGSR_EL1: Selected Error Record Group Status Register

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ERXMISC0_EL1: Selected Error Record Miscellaneous Register 0

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ERXMISC1_EL1: Selected Error Record Miscellaneous Register 1

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ERXMISC2_EL1: Selected Error Record Miscellaneous Register 2

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ERXMISC3_EL1: Selected Error Record Miscellaneous Register 3

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ERXSTATUS_EL1: Selected Error Record Primary Status Register

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ESR_EL1: Exception Syndrome Register (EL1)

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ESR_EL2: Exception Syndrome Register (EL2)

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ESR_EL3: Exception Syndrome Register (EL3)

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FGDTP<n>_EL1: Fine Grained Dynamic Traps, Privileged (EL1)

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FGDTP<n>_EL2: Fine Grained Dynamic Traps, Privileged (EL2)

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FGDTP<n>_EL3: Fine Grained Dynamic Traps, Privileged (EL3)

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FGDTU<n>_EL1: Fine Grained Dynamic Traps, Unprivileged (EL1)

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FGDTU<n>_EL2: Fine Grained Dynamic Traps, Unprivileged (EL2)

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FGWTE3_EL3: Fine-Grained Write Traps EL3

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GCSCRE0_EL1: Guarded Control Stack Control Register (EL0)

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GCSCR_EL1: Guarded Control Stack Control Register (EL1)

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GCSCR_EL2: Guarded Control Stack Control Register (EL2)

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GCSCR_EL3: Guarded Control Stack Control Register (EL3)

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GCSPR_EL0: Guarded Control Stack Pointer Register (EL0)

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GCSPR_EL1: Guarded Control Stack Pointer Register (EL1)

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GCSPR_EL2: Guarded Control Stack Pointer Register (EL2)

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GCSPR_EL3: Guarded Control Stack Pointer Register (EL3)

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GMID_EL1: Multiple tag transfer ID Register

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GPCBW_EL3: Granule Protection Check Bypass Window Register (EL3)

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GPCCR_EL3: Granule Protection Check Control Register (EL3)

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GPTBR_EL3: Granule Protection Table Base Register

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HACDBSBR_EL2: Hardware Accelerator for Cleaning Dirty State Base Register

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HACDBSCONS_EL2: Hardware Accelerator for Cleaning Dirty State Consumer Register

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HACR_EL2: Hypervisor Auxiliary Control Register

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HAFGRTR_EL2: Hypervisor Activity Monitors Fine-Grained Read Trap Register

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HDBSSBR_EL2: Hardware Dirty State Tracking Structure Base Register

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HDBSSPROD_EL2: Hardware Dirty State Tracking Structure Producer Register

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HDFGRTR2_EL2: Hypervisor Debug Fine-Grained Read Trap Register 2

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HDFGRTR_EL2: Hypervisor Debug Fine-Grained Read Trap Register

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HDFGWTR2_EL2: Hypervisor Debug Fine-Grained Write Trap Register 2

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HDFGWTR_EL2: Hypervisor Debug Fine-Grained Write Trap Register

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HFGITR2_EL2: Hypervisor Fine-Grained Instruction Trap Register 2

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HFGRTR2_EL2: Hypervisor Fine-Grained Read Trap Register 2

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HFGRTR_EL2: Hypervisor Fine-Grained Read Trap Register

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HFGWTR2_EL2: Hypervisor Fine-Grained Write Trap Register 2

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HFGWTR_EL2: Hypervisor Fine-Grained Write Trap Register

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HPFAR_EL2: Hypervisor IPA Fault Address Register

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HSTR_EL2: Hypervisor System Trap Register

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ICC_AP0R<n>_EL1: Interrupt Controller Active Priorities Group 0 Registers

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ICC_AP1R<n>_EL1: Interrupt Controller Active Priorities Group 1 Registers

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ICC_APR_EL1: Interrupt Controller Physical Active Priorities Register (EL1)

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ICC_APR_EL3: Interrupt Controller Physical Active Priorities Register for EL3

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ICC_ASGI1R_EL1: Interrupt Controller Alias Software Generated Interrupt Group 1 Register

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ICC_BPR0_EL1: Interrupt Controller Binary Point Register 0

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ICC_BPR1_EL1: Interrupt Controller Binary Point Register 1

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ICC_CR0_EL1: Interrupt Controller Physical Control Register (EL1)

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ICC_CR0_EL3: Interrupt Controller Physical Control Register (EL3)

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ICC_CTLR_EL1: Interrupt Controller Control Register (EL1)

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ICC_CTLR_EL3: Interrupt Controller Control Register (EL3)

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ICC_DOMHPPIR_EL3: Interrupt Controller Domain Highest Priority Pending Interrupt Register

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ICC_EOIR0_EL1: Interrupt Controller End Of Interrupt Register 0

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ICC_EOIR1_EL1: Interrupt Controller End Of Interrupt Register 1

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ICC_HAPR_EL1: Interrupt Controller Physical Highest Active Priority Register

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ICC_HPPIR0_EL1: Interrupt Controller Highest Priority Pending Interrupt Register 0

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ICC_HPPIR1_EL1: Interrupt Controller Highest Priority Pending Interrupt Register 1

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ICC_HPPIR_EL1: Interrupt Controller Physical Highest Priority Pending Interrupt Register (EL1)

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ICC_HPPIR_EL3: Interrupt Controller Physical Highest Priority Pending Interrupt Register (EL3)

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ICC_IAFFIDR_EL1: Interrupt Controller PE Interrupt Affinity ID Register

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ICC_IAR0_EL1: Interrupt Controller Interrupt Acknowledge Register 0

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ICC_IAR1_EL1: Interrupt Controller Interrupt Acknowledge Register 1

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ICC_ICSR_EL1: Interrupt Controller Interrupt Configuration and State Register

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ICC_IDR0_EL1: Interrupt Controller ID Register 0

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ICC_IGRPEN0_EL1: Interrupt Controller Interrupt Group 0 Enable Register

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ICC_IGRPEN1_EL1: Interrupt Controller Interrupt Group 1 Enable Register

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ICC_IGRPEN1_EL3: Interrupt Controller Interrupt Group 1 Enable Register (EL3)

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ICC_NMIAR1_EL1: Interrupt Controller Non-maskable Interrupt Acknowledge Register 1

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ICC_PCR_EL1: Interrupt Controller Physical Interrupt Priority Control Register (EL1)

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ICC_PCR_EL3: Interrupt Controller Interrupt Priority Control Register (EL3)

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ICC_PMR_EL1: Interrupt Controller Interrupt Priority Mask Register

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ICC_PPI_CACTIVER<n>_EL1: Interrupt Controller Physical PPI Clear Active Registers

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ICC_PPI_CPENDR<n>_EL1: Interrupt Controller Physical PPI Clear Pending State Registers

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ICC_PPI_HMR<n>_EL1: Interrupt Controller Physical PPI Handling mode Registers

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ICC_PPI_SACTIVER<n>_EL1: Interrupt Controller Physical PPI Set Active Registers

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ICC_PPI_SPENDR<n>_EL1: Interrupt Controller Physical PPI Set Pending State Registers

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ICC_RPR_EL1: Interrupt Controller Running Priority Register

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ICC_SGI0R_EL1: Interrupt Controller Software Generated Interrupt Group 0 Register

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ICC_SGI1R_EL1: Interrupt Controller Software Generated Interrupt Group 1 Register

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ICC_SRE_EL1: Interrupt Controller System Register Enable Register (EL1)

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ICC_SRE_EL2: Interrupt Controller System Register Enable Register (EL2)

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ICC_SRE_EL3: Interrupt Controller System Register Enable Register (EL3)

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ICH_AP0R<n>_EL2: Interrupt Controller Hyp Active Priorities Group 0 Registers

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ICH_AP1R<n>_EL2: Interrupt Controller Hyp Active Priorities Group 1 Registers

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ICH_APR_EL2: Interrupt Controller Active Virtual Priorities Register

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ICH_EISR_EL2: Interrupt Controller End of Interrupt Status Register

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ICH_ELRSR_EL2: Interrupt Controller Empty List Register Status Register

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ICH_HCR_EL2: Interrupt Controller Hyp Control Register

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ICH_HFGITR_EL2: Hypervisor GIC Fine-Grained Instruction Trap Register

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ICH_HFGRTR_EL2: Hypervisor GIC Fine-Grained Read Trap Register

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ICH_HFGWTR_EL2: Hypervisor GIC Fine-Grained Write Trap Register

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ICH_HPPIR_EL2: Interrupt Controller Hypervisor Highest Priority Pending Interrupt Register

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ICH_MISR_EL2: Interrupt Controller Maintenance Interrupt State Register

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ICH_PPI_PENDR<n>_EL2: Interrupt Controller Virtual Interrupt Pending State Registers

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ICH_VCTLR_EL2: Interrupt Controller Virtual CPU interface Control Register

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ICH_VMCR_EL2: Interrupt Controller Virtual Machine Control Register

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ICH_VTR_EL2: Interrupt Controller VGIC Type Register

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ICV_AP0R<n>_EL1: Interrupt Controller Virtual Active Priorities Group 0 Registers

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ICV_AP1R<n>_EL1: Interrupt Controller Virtual Active Priorities Group 1 Registers

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ICV_APR_EL1: Interrupt Controller Virtual Active Priorities Register

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ICV_BPR0_EL1: Interrupt Controller Virtual Binary Point Register 0

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ICV_BPR1_EL1: Interrupt Controller Virtual Binary Point Register 1

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ICV_CR0_EL1: Interrupt Controller EL1 Virtual Control Register

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ICV_CTLR_EL1: Interrupt Controller Virtual Control Register

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ICV_DIR_EL1: Interrupt Controller Deactivate Virtual Interrupt Register

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ICV_EOIR0_EL1: Interrupt Controller Virtual End Of Interrupt Register 0

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ICV_EOIR1_EL1: Interrupt Controller Virtual End Of Interrupt Register 1

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ICV_HAPR_EL1: Interrupt Controller Virtual Highest Active Priority Register

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ICV_HPPIR0_EL1: Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0

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ICV_HPPIR1_EL1: Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1

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ICV_HPPIR_EL1: Interrupt Controller Virtual Highest Priority Pending Interrupt Register

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ICV_IAR0_EL1: Interrupt Controller Virtual Interrupt Acknowledge Register 0

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ICV_IAR1_EL1: Interrupt Controller Virtual Interrupt Acknowledge Register 1

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ICV_IGRPEN0_EL1: Interrupt Controller Virtual Interrupt Group 0 Enable Register

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ICV_IGRPEN1_EL1: Interrupt Controller Virtual Interrupt Group 1 Enable Register

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ICV_NMIAR1_EL1: Interrupt Controller Virtual Non-maskable Interrupt Acknowledge Register 1

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ICV_PCR_EL1: Interrupt Controller Virtual Interrupt Priority Control Register

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ICV_PMR_EL1: Interrupt Controller Virtual Interrupt Priority Mask Register

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ICV_PPI_CACTIVER<n>_EL1: Interrupt Controller Virtual PPI Clear Active Registers

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ICV_PPI_CPENDR<n>_EL1: Interrupt Controller Virtual PPI Clear Pending State Registers

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ICV_PPI_ENABLER<n>_EL1: Interrupt Controller Virtual PPI Clear Enable Registers

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ICV_PPI_HMR<n>_EL1: Interrupt Controller Virtual PPI Handling mode Registers

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ICV_PPI_SACTIVER<n>_EL1: Interrupt Controller Virtual PPI Set Active Registers

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ICV_PPI_SPENDR<n>_EL1: Interrupt Controller Virtual PPI Set Pending State Registers

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ICV_RPR_EL1: Interrupt Controller Virtual Running Priority Register

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ID_AA64AFR0_EL1: AArch64 Auxiliary Feature Register 0

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ID_AA64AFR1_EL1: AArch64 Auxiliary Feature Register 1

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ID_AA64DFR0_EL1: AArch64 Debug Feature Register 0

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ID_AA64DFR1_EL1: AArch64 Debug Feature Register 1

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ID_AA64DFR2_EL1: AArch64 Debug Feature Register 2

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ID_AA64FPFR0_EL1: AArch64 Floating-point Feature Register 0

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ID_AA64ISAR0_EL1: AArch64 Instruction Set Attribute Register 0

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ID_AA64ISAR1_EL1: AArch64 Instruction Set Attribute Register 1

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ID_AA64ISAR2_EL1: AArch64 Instruction Set Attribute Register 2

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ID_AA64ISAR3_EL1: AArch64 Instruction Set Attribute Register 3

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ID_AA64MMFR0_EL1: AArch64 Memory Model Feature Register 0

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ID_AA64MMFR1_EL1: AArch64 Memory Model Feature Register 1

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ID_AA64MMFR2_EL1: AArch64 Memory Model Feature Register 2

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ID_AA64MMFR3_EL1: AArch64 Memory Model Feature Register 3

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ID_AA64MMFR4_EL1: AArch64 Memory Model Feature Register 4

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ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0

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ID_AA64PFR1_EL1: AArch64 Processor Feature Register 1

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ID_AA64PFR2_EL1: AArch64 Processor Feature Register 2

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ID_AA64SMFR0_EL1: SME Feature ID Register 0

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ID_AA64ZFR0_EL1: SVE Feature ID Register 0

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ID_AFR0_EL1: AArch32 Auxiliary Feature Register 0

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ID_DFR0_EL1: AArch32 Debug Feature Register 0

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ID_DFR1_EL1: AArch32 Debug Feature Register 1

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ID_ISAR0_EL1: AArch32 Instruction Set Attribute Register 0

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ID_ISAR1_EL1: AArch32 Instruction Set Attribute Register 1

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ID_ISAR2_EL1: AArch32 Instruction Set Attribute Register 2

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ID_ISAR3_EL1: AArch32 Instruction Set Attribute Register 3

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ID_ISAR4_EL1: AArch32 Instruction Set Attribute Register 4

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ID_ISAR5_EL1: AArch32 Instruction Set Attribute Register 5

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ID_ISAR6_EL1: AArch32 Instruction Set Attribute Register 6

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ID_MMFR0_EL1: AArch32 Memory Model Feature Register 0

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ID_MMFR1_EL1: AArch32 Memory Model Feature Register 1

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ID_MMFR2_EL1: AArch32 Memory Model Feature Register 2

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ID_MMFR3_EL1: AArch32 Memory Model Feature Register 3

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ID_MMFR4_EL1: AArch32 Memory Model Feature Register 4

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ID_MMFR5_EL1: AArch32 Memory Model Feature Register 5

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ID_PFR0_EL1: AArch32 Processor Feature Register 0

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ID_PFR1_EL1: AArch32 Processor Feature Register 1

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ID_PFR2_EL1: AArch32 Processor Feature Register 2

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IFSR32_EL2: Instruction Fault Status Register (EL2)

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IRTBRP_EL1: Instruction Region Table Base Register, Privileged (EL1)

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IRTBRP_EL2: Instruction Region Table Base Register, Privileged (EL2)

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IRTBRP_EL3: Instruction Region Table Base Register, Privileged (EL3)

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IRTBRU_EL1: Instruction Region Table Base Register, Unprivileged (EL1)

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IRTBRU_EL2: Instruction Region Table Base Register, Unprivileged (EL2)

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LDSTT_EL1: Load and Store Unprivileged Context register (EL1)

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LDSTT_EL2: Load and Store Unprivileged Context register (EL2)

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MAIR2_EL1: Extended Memory Attribute Indirection Register (EL1)

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MAIR2_EL2: Extended Memory Attribute Indirection Register (EL2)

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MAIR2_EL3: Extended Memory Attribute Indirection Register (EL3)

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MAIR_EL1: Memory Attribute Indirection Register (EL1)

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MAIR_EL2: Memory Attribute Indirection Register (EL2)

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MAIR_EL3: Memory Attribute Indirection Register (EL3)

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MDCCINT_EL1: Monitor DCC Interrupt Enable Register

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MDCR_EL2: Monitor Debug Configuration Register (EL2)

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MDCR_EL3: Monitor Debug Configuration Register (EL3)

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MDRAR_EL1: Monitor Debug ROM Address Register

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MDSCR_EL1: Monitor Debug System Control Register

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MDSELR_EL1: Breakpoint and Watchpoint Selection Register

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MDSTEPOP_EL1: Monitor Debug Step Opcode Register

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MECID_A0_EL2: Alternate MECID for EL2 and EL2&0 translation regimes

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MECID_A1_EL2: Alternate MECID for EL2&0 translation regimes.

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MECID_P0_EL2: Primary MECID for EL2 and EL2&0 translation regimes

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MECID_P1_EL2: Primary MECID for EL2&0 translation regimes

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MECID_RL_A_EL3: Realm PA space Alternate MECID for EL3 stage 1 translation regime

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MFAR_EL3: Physical Fault Address Register (EL3)

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MPAMBW0_EL1: MPAM PE-side Maximum-bandwidth Control Register (EL0)

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MPAMBW1_EL1: MPAM PE-side Maximum-bandwidth Control Register (EL1)

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MPAMBW2_EL2: MPAM PE-side Maximum-bandwidth Control Register (EL2)

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MPAMBW3_EL3: MPAM PE-side Maximum-bandwidth Control Register (EL3)

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MPAMBWIDR_EL1: MPAM PE-side Bandwidth Controls ID Register

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MPAMBWSM_EL1: MPAM Streaming Mode Bandwidth Control Register (EL1)

# topic.topics[].topics[].label
MPAMCTL_EL1: MPAM Control Register (EL1)

# topic.topics[].topics[].label
MPAMCTL_EL2: MPAM Control Register (EL2)

# topic.topics[].topics[].label
MPAMCTL_EL3: MPAM Control Register (EL3)

# topic.topics[].topics[].label
MPAMHCR_EL2: MPAM Hypervisor Control Register (EL2)

# topic.topics[].topics[].label
MPAMSM_EL1: MPAM Streaming Mode Register

# topic.topics[].topics[].label
MPAMVIDCR_EL2: MPAM Virtual Identifier Control Register

# topic.topics[].topics[].label
MPAMVIDSR_EL2: MPAM Virtual Identifier Status Register

# topic.topics[].topics[].label
MPAMVPM0_EL2: MPAM Virtual PARTID Mapping Register 0

# topic.topics[].topics[].label
MPAMVPM1_EL2: MPAM Virtual PARTID Mapping Register 1

# topic.topics[].topics[].label
MPAMVPM2_EL2: MPAM Virtual PARTID Mapping Register 2

# topic.topics[].topics[].label
MPAMVPM3_EL2: MPAM Virtual PARTID Mapping Register 3

# topic.topics[].topics[].label
MPAMVPM4_EL2: MPAM Virtual PARTID Mapping Register 4

# topic.topics[].topics[].label
MPAMVPM5_EL2: MPAM Virtual PARTID Mapping Register 5

# topic.topics[].topics[].label
MPAMVPM6_EL2: MPAM Virtual PARTID Mapping Register 6

# topic.topics[].topics[].label
MPAMVPM7_EL2: MPAM Virtual PARTID Mapping Register 7

# topic.topics[].topics[].label
MPAMVPMV_EL2: MPAM Virtual Partition Mapping Valid Register

# topic.topics[].topics[].label
MVFR0_EL1: AArch32 Media and VFP Feature Register 0

# topic.topics[].topics[].label
MVFR1_EL1: AArch32 Media and VFP Feature Register 1

# topic.topics[].topics[].label
MVFR2_EL1: AArch32 Media and VFP Feature Register 2

# topic.topics[].topics[].label
NVHCRMASK_EL2: Nested Virtual Hypervisor Configuration Masking Register

# topic.topics[].topics[].label
NVHCRXMASK_EL2: Nested Virtual Extended Hypervisor Configuration Masking Register

# topic.topics[].topics[].label
NVHCRX_EL2: Nested Virtual Extended Hypervisor Configuration Register

# topic.topics[].topics[].label
NVHCR_EL2: Nested Virtual Hypervisor Configuration Register

# topic.topics[].topics[].label
OSDTRRX_EL1: OS Lock Data Transfer Register, Receive

# topic.topics[].topics[].label
OSDTRTX_EL1: OS Lock Data Transfer Register, Transmit

# topic.topics[].topics[].label
OSECCR_EL1: OS Lock Exception Catch Control Register

# topic.topics[].topics[].label
PFAR_EL1: Physical Fault Address Register (EL1)

# topic.topics[].topics[].label
PFAR_EL2: Physical Fault Address Register (EL2)

# topic.topics[].topics[].label
PIRE0_EL1: Permission Indirection Register 0 (EL1)

# topic.topics[].topics[].label
PIRE0_EL2: Permission Indirection Register 0 (EL2)

# topic.topics[].topics[].label
PIR_EL1: Permission Indirection Register 1 (EL1)

# topic.topics[].topics[].label
PIR_EL2: Permission Indirection Register 2 (EL2)

# topic.topics[].topics[].label
PIR_EL3: Permission Indirection Register 3 (EL3)

# topic.topics[].topics[].label
PMBIDR_EL1: Profiling Buffer ID Register

# topic.topics[].topics[].label
PMBLIMITR_EL1: Profiling Buffer Limit Address Register

# topic.topics[].topics[].label
PMBMAR_EL1: Profiling Buffer Memory Attribute Register

# topic.topics[].topics[].label
PMBPTR_EL1: Profiling Buffer Write Pointer Register

# topic.topics[].topics[].label
PMBSR_EL1: Profiling Buffer Status/syndrome Register (EL1)

# topic.topics[].topics[].label
PMBSR_EL2: Profiling Buffer Syndrome Register (EL2)

# topic.topics[].topics[].label
PMBSR_EL3: Profiling Buffer Syndrome Register (EL3)

# topic.topics[].topics[].label
PMCCFILTR_EL0: Performance Monitors Cycle Count Filter Register

# topic.topics[].topics[].label
PMCCNTR_EL0: Performance Monitors Cycle Count Register

# topic.topics[].topics[].label
PMCCNTSVR_EL1: Performance Monitors Cycle Count Saved Value Register

# topic.topics[].topics[].label
PMCEID0_EL0: Performance Monitors Common Event Identification Register 0

# topic.topics[].topics[].label
PMCEID1_EL0: Performance Monitors Common Event Identification Register 1

# topic.topics[].topics[].label
PMCNTENCLR_EL0: Performance Monitors Count Enable Clear Register

# topic.topics[].topics[].label
PMCNTENSET_EL0: Performance Monitors Count Enable Set Register

# topic.topics[].topics[].label
PMCR_EL0: Performance Monitors Control Register

# topic.topics[].topics[].label
PMECR_EL1: Performance Monitors Extended Control Register (EL1)

# topic.topics[].topics[].label
PMEVCNTR<n>_EL0: Performance Monitors Event Count Registers

# topic.topics[].topics[].label
PMEVCNTSVR<n>_EL1: Performance Monitors Event Count Saved Value Registers

# topic.topics[].topics[].label
PMEVTYPER<n>_EL0: Performance Monitors Event Type Registers

# topic.topics[].topics[].label
PMIAR_EL1: Performance Monitors Instruction Address Register

# topic.topics[].topics[].label
PMICFILTR_EL0: Performance Monitors Instruction Counter Filter Register

# topic.topics[].topics[].label
PMICNTSVR_EL1: Performance Monitors Instruction Count Saved Value Register

# topic.topics[].topics[].label
PMINTENCLR_EL1: Performance Monitors Interrupt Enable Clear Register

# topic.topics[].topics[].label
PMINTENSET_EL1: Performance Monitors Interrupt Enable Set Register

# topic.topics[].topics[].label
PMOVSCLR_EL0: Performance Monitors Overflow Flag Status Clear Register

# topic.topics[].topics[].label
PMOVSSET_EL0: Performance Monitors Overflow Flag Status Set Register

# topic.topics[].topics[].label
PMSCR_EL1: Statistical Profiling Control Register (EL1)

# topic.topics[].topics[].label
PMSCR_EL2: Statistical Profiling Control Register (EL2)

# topic.topics[].topics[].label
PMSDSFR_EL1: Sampling Data Source Filter Register

# topic.topics[].topics[].label
PMSELR_EL0: Performance Monitors Event Counter Selection Register

# topic.topics[].topics[].label
PMSEVFR_EL1: Sampling Event Filter Register

# topic.topics[].topics[].label
PMSFCR_EL1: Sampling Filter Control Register

# topic.topics[].topics[].label
PMSICR_EL1: Sampling Interval Counter Register

# topic.topics[].topics[].label
PMSIDR_EL1: Sampling Profiling ID Register

# topic.topics[].topics[].label
PMSIRR_EL1: Sampling Interval Reload Register

# topic.topics[].topics[].label
PMSLATFR_EL1: Sampling Latency Filter Register

# topic.topics[].topics[].label
PMSNEVFR_EL1: Sampling Inverted Event Filter Register

# topic.topics[].topics[].label
PMSSCR_EL1: Performance Monitors Snapshot Status and Capture Register

# topic.topics[].topics[].label
PMUACR_EL1: Performance Monitors User Access Control Register

# topic.topics[].topics[].label
PMUSERENR_EL0: Performance Monitors User Enable Register

# topic.topics[].topics[].label
PMXEVCNTR_EL0: Performance Monitors Selected Event Count Register

# topic.topics[].topics[].label
PMXEVTYPER_EL0: Performance Monitors Selected Event Type Register

# topic.topics[].topics[].label
PMZR_EL0: Performance Monitors Zero with Mask

# topic.topics[].topics[].label
POR_EL0: Permission Overlay Register 0 (EL0)

# topic.topics[].topics[].label
POR_EL1: Permission Overlay Register 1 (EL1)

# topic.topics[].topics[].label
POR_EL2: Permission Overlay Register 2 (EL2)

# topic.topics[].topics[].label
POR_EL3: Permission Overlay Register 3 (EL3)

# topic.topics[].topics[].label
RCWMASK_EL1: Read Check Write Instruction Mask (EL1)

# topic.topics[].topics[].label
RCWSMASK_EL1: Software Read Check Write Instruction Mask (EL1)

# topic.topics[].topics[].label
RGSR_EL1: Random Allocation Tag Seed Register.

# topic.topics[].topics[].label
RMR_EL1: Reset Management Register (EL1)

# topic.topics[].topics[].label
RMR_EL2: Reset Management Register (EL2)

# topic.topics[].topics[].label
RMR_EL3: Reset Management Register (EL3)

# topic.topics[].topics[].label
RVBAR_EL1: Reset Vector Base Address Register (if EL2 and EL3 not implemented)

# topic.topics[].topics[].label
RVBAR_EL2: Reset Vector Base Address Register (if EL3 not implemented)

# topic.topics[].topics[].label
RVBAR_EL3: Reset Vector Base Address Register (if EL3 implemented)

# topic.topics[].topics[].label
S2PIR_EL2: Stage 2 Permission Indirection Register (EL2)

# topic.topics[].topics[].label
S2POR_EL1: Stage 2 Permission Overlay Register (EL1)

# topic.topics[].topics[].label
S3_<op1>_<Cn>_<Cm>_<op2>: IMPLEMENTATION DEFINED Registers

# topic.topics[].topics[].label
SCTLR2MASK_EL1: Extended System Control Masking Register (EL1)

# topic.topics[].topics[].label
SCTLR2MASK_EL2: Extended System Control Masking Register (EL2)

# topic.topics[].topics[].label
SCTLR2_EL1: System Control Register (EL1)

# topic.topics[].topics[].label
SCTLR2_EL2: System Control Register (EL2)

# topic.topics[].topics[].label
SCTLR2_EL3: System Control Register (EL3)

# topic.topics[].topics[].label
SCTLRMASK_EL1: System Control Masking Register (EL1)

# topic.topics[].topics[].label
SCTLRMASK_EL2: System Control Masking Register (EL2)

# topic.topics[].topics[].label
SCTLR_EL1: System Control Register (EL1)

# topic.topics[].topics[].label
SCTLR_EL2: System Control Register (EL2)

# topic.topics[].topics[].label
SCTLR_EL3: System Control Register (EL3)

# topic.topics[].topics[].label
SCXTNUM_EL0: EL0 Read/Write Software Context Number

# topic.topics[].topics[].label
SCXTNUM_EL1: EL1 Read/Write Software Context Number

# topic.topics[].topics[].label
SCXTNUM_EL2: EL2 Read/Write Software Context Number

# topic.topics[].topics[].label
SCXTNUM_EL3: EL3 Read/Write Software Context Number

# topic.topics[].topics[].label
SDER32_EL2: AArch32 Secure Debug Enable Register

# topic.topics[].topics[].label
SDER32_EL3: AArch32 Secure Debug Enable Register

# topic.topics[].topics[].label
SMPRIMAP_EL2: Streaming Mode Priority Mapping Register

# topic.topics[].topics[].label
SMPRI_EL1: Streaming Mode Priority Register

# topic.topics[].topics[].label
SPMACCESSR_EL1: System Performance Monitors Access Register (EL1)

# topic.topics[].topics[].label
SPMACCESSR_EL2: System Performance Monitors Access Register (EL2)

# topic.topics[].topics[].label
SPMACCESSR_EL3: System Performance Monitors Access Register (EL3)

# topic.topics[].topics[].label
SPMCGCR<n>_EL1: System PMU Counter Group Configuration Registers

# topic.topics[].topics[].label
SPMCNTENCLR_EL0: System Performance Monitors Count Enable Clear Register

# topic.topics[].topics[].label
SPMCNTENSET_EL0: System Performance Monitors Count Enable Set Register

# topic.topics[].topics[].label
SPMCR_EL0: System Performance Monitor Control Register

# topic.topics[].topics[].label
SPMDEVAFF_EL1: System Performance Monitors Device Affinity Register

# topic.topics[].topics[].label
SPMDEVARCH_EL1: System Performance Monitors Device Architecture Register

# topic.topics[].topics[].label
SPMEVCNTR<n>_EL0: System Performance Monitors Event Count Register

# topic.topics[].topics[].label
SPMEVFILT2R<n>_EL0: System Performance Monitors Event Filter Control Register 2

# topic.topics[].topics[].label
SPMEVFILTR<n>_EL0: System Performance Monitors Event Filter Control Register

# topic.topics[].topics[].label
SPMEVTYPER<n>_EL0: System Performance Monitors Event Type Register

# topic.topics[].topics[].label
SPMINTENCLR_EL1: System Performance Monitors Interrupt Enable Clear Register

# topic.topics[].topics[].label
SPMINTENSET_EL1: System Performance Monitors Interrupt Enable Set Register

# topic.topics[].topics[].label
SPMOVSCLR_EL0: System Performance Monitors Overflow Flag Status Clear Register

# topic.topics[].topics[].label
SPMOVSSET_EL0: System Performance Monitors Overflow Flag Status Set Register

# topic.topics[].topics[].label
SPMROOTCR_EL3: System Performance Monitors Root and Realm Control Register

# topic.topics[].topics[].label
SPMSCR_EL1: System Performance Monitors Secure Control Register

# topic.topics[].topics[].label
SPMSELR_EL0: System Performance Monitors Select Register

# topic.topics[].topics[].label
SPMZR_EL0: System Performance Monitors Zero with Mask

# topic.topics[].topics[].label
SPSR_EL1: Saved Program Status Register (EL1)

# topic.topics[].topics[].label
SPSR_EL2: Saved Program Status Register (EL2)

# topic.topics[].topics[].label
SPSR_EL3: Saved Program Status Register (EL3)

# topic.topics[].topics[].label
SPSR_abt: Saved Program Status Register (Abort mode)

# topic.topics[].topics[].label
SPSR_fiq: Saved Program Status Register (FIQ mode)

# topic.topics[].topics[].label
SPSR_irq: Saved Program Status Register (IRQ mode)

# topic.topics[].topics[].label
SPSR_und: Saved Program Status Register (Undefined mode)

# topic.topics[].topics[].label
TCR2MASK_EL1: Extended Translation Control Masking Register (EL1)

# topic.topics[].topics[].label
TCR2MASK_EL2: Extended Translation Control Masking Register (EL2)

# topic.topics[].topics[].label
TCR2_EL1: Extended Translation Control Register (EL1)

# topic.topics[].topics[].label
TCR2_EL2: Extended Translation Control Register (EL2)

# topic.topics[].topics[].label
TCRMASK_EL1: Translation Control Masking Register (EL1)

# topic.topics[].topics[].label
TCRMASK_EL2: Translation Control Masking Register (EL2)

# topic.topics[].topics[].label
TCR_EL1: Translation Control Register (EL1)

# topic.topics[].topics[].label
TCR_EL2: Translation Control Register (EL2)

# topic.topics[].topics[].label
TCR_EL3: Translation Control Register (EL3)

# topic.topics[].topics[].label
TFSRE0_EL1: Tag Fault Status Register (EL0).

# topic.topics[].topics[].label
TFSR_EL1: Tag Fault Status Register (EL1)

# topic.topics[].topics[].label
TFSR_EL2: Tag Fault Status Register (EL2)

# topic.topics[].topics[].label
TFSR_EL3: Tag Fault Status Register (EL3)

# topic.topics[].topics[].label
TLBIDIDR_EL1: TLBI Domains Identification Register (EL1)

# topic.topics[].topics[].label
TPIDR2_EL0: EL0 Read/Write Software Thread ID Register 2

# topic.topics[].topics[].label
TPIDR3_EL0: EL0 Read/Write Software Thread ID Register 3

# topic.topics[].topics[].label
TPIDR3_EL1: EL1 Software Thread ID Register 3

# topic.topics[].topics[].label
TPIDR3_EL2: EL2 Software Thread ID Register 3

# topic.topics[].topics[].label
TPIDR3_EL3: EL3 Software Thread ID Register 3

# topic.topics[].topics[].label
TPIDRRO_EL0: EL0 Read-Only Software Thread ID Register

# topic.topics[].topics[].label
TPIDR_EL0: EL0 Read/Write Software Thread ID Register

# topic.topics[].topics[].label
TPIDR_EL1: EL1 Software Thread ID Register

# topic.topics[].topics[].label
TPIDR_EL2: EL2 Software Thread ID Register

# topic.topics[].topics[].label
TPIDR_EL3: EL3 Software Thread ID Register

# topic.topics[].topics[].label
TPMAX0_EL0: Thread-Private State Upper Limit 0 (EL0)

# topic.topics[].topics[].label
TPMAX0_EL1: Thread-Private State Upper Limit 0 (EL1)

# topic.topics[].topics[].label
TPMAX0_EL2: Thread-Private State Upper Limit 0 (EL2)

# topic.topics[].topics[].label
TPMAX1_EL0: Thread-Private State Upper Limit 1 (EL0)

# topic.topics[].topics[].label
TPMAX1_EL1: Thread-Private State Upper Limit 1 (EL1)

# topic.topics[].topics[].label
TPMAX1_EL2: Thread-Private State Upper Limit 1 (EL2)

# topic.topics[].topics[].label
TPMIN0_EL0: Thread-Private State Lower Limit 0 (EL0)

# topic.topics[].topics[].label
TPMIN0_EL1: Thread-Private State Lower Limit 0 (EL1)

# topic.topics[].topics[].label
TPMIN0_EL2: Thread-Private State Lower Limit 0 (EL2)

# topic.topics[].topics[].label
TPMIN1_EL0: Thread-Private State Lower Limit 1 (EL0)

# topic.topics[].topics[].label
TPMIN1_EL1: Thread-Private State Lower Limit 1 (EL1)

# topic.topics[].topics[].label
TPMIN1_EL2: Thread-Private State Lower Limit 1 (EL2)

# topic.topics[].topics[].label
TRBBASER_EL1: Trace Buffer Base Address Register

# topic.topics[].topics[].label
TRBLIMITR_EL1: Trace Buffer Limit Address Register

# topic.topics[].topics[].label
TRBMAR_EL1: Trace Buffer Memory Attribute Register

# topic.topics[].topics[].label
TRBMPAM_EL1: Trace Buffer MPAM Configuration Register

# topic.topics[].topics[].label
TRBPTR_EL1: Trace Buffer Write Pointer Register

# topic.topics[].topics[].label
TRBSR_EL1: Trace Buffer Status/syndrome Register (EL1)

# topic.topics[].topics[].label
TRBSR_EL2: Trace Buffer Syndrome Register (EL2)

# topic.topics[].topics[].label
TRBSR_EL3: Trace Buffer Syndrome Register (EL3)

# topic.topics[].topics[].label
TRBTRG_EL1: Trace Buffer Trigger Counter Register

# topic.topics[].topics[].label
TRCACATR<n>: Trace Address Comparator Access Type Register <n>

# topic.topics[].topics[].label
TRCACVR<n>: Trace Address Comparator Value Register <n>

# topic.topics[].topics[].label
TRCAUXCTLR: Trace Auxiliary Control Register

# topic.topics[].topics[].label
TRCBBCTLR: Trace Branch Broadcast Control Register

# topic.topics[].topics[].label
TRCCCCTLR: Trace Cycle Count Control Register

# topic.topics[].topics[].label
TRCCIDCCTLR0: Trace Context Identifier Comparator Control Register 0

# topic.topics[].topics[].label
TRCCIDCCTLR1: Trace Context Identifier Comparator Control Register 1

# topic.topics[].topics[].label
TRCCIDCVR<n>: Trace Context Identifier Comparator Value Registers <n>

# topic.topics[].topics[].label
TRCCLAIMCLR: Trace Claim Tag Clear Register

# topic.topics[].topics[].label
TRCCLAIMSET: Trace Claim Tag Set Register

# topic.topics[].topics[].label
TRCCNTCTLR<n>: Trace Counter Control Register <n>

# topic.topics[].topics[].label
TRCCNTRLDVR<n>: Trace Counter Reload Value Register <n>

# topic.topics[].topics[].label
TRCCNTVR<n>: Trace Counter Value Register <n>

# topic.topics[].topics[].label
TRCDEVARCH: Trace Device Architecture Register

# topic.topics[].topics[].label
TRCDEVID: Trace Device Configuration Register

# topic.topics[].topics[].label
TRCEVENTCTL0R: Trace Event Control 0 Register

# topic.topics[].topics[].label
TRCEVENTCTL1R: Trace Event Control 1 Register

# topic.topics[].topics[].label
TRCEXTINSELR<n>: Trace External Input Select Register <n>

# topic.topics[].topics[].label
TRCIMSPEC<n>: Trace IMP DEF Register <n>

# topic.topics[].topics[].label
TRCITECR_EL1: Instrumentation Trace Control Register (EL1)

# topic.topics[].topics[].label
TRCITECR_EL2: Instrumentation Trace Control Register (EL2)

# topic.topics[].topics[].label
TRCITEEDCR: Instrumentation Trace Extension External Debug Control Register

# topic.topics[].topics[].label
TRCPRGCTLR: Trace Programming Control Register

# topic.topics[].topics[].label
TRCQCTLR: Trace Q Element Control Register

# topic.topics[].topics[].label
TRCRSCTLR<n>: Trace Resource Selection Control Register <n>

# topic.topics[].topics[].label
TRCSEQEVR<n>: Trace Sequencer State Transition Control Register <n>

# topic.topics[].topics[].label
TRCSEQRSTEVR: Trace Sequencer Reset Control Register

# topic.topics[].topics[].label
TRCSEQSTR: Trace Sequencer State Register

# topic.topics[].topics[].label
TRCSSCCR<n>: Trace Single-shot Comparator Control Register <n>

# topic.topics[].topics[].label
TRCSSCSR<n>: Trace Single-shot Comparator Control Status Register <n>

# topic.topics[].topics[].label
TRCSSPCICR<n>: Trace Single-shot Processing Element Comparator Input Control Register <n>

# topic.topics[].topics[].label
TRCSTALLCTLR: Trace Stall Control Register

# topic.topics[].topics[].label
TRCSYNCPR: Trace Synchronization Period Register

# topic.topics[].topics[].label
TRCTSCTLR: Trace Timestamp Control Register

# topic.topics[].topics[].label
TRCVICTLR: Trace ViewInst Main Control Register

# topic.topics[].topics[].label
TRCVIIECTLR: Trace ViewInst Include/Exclude Control Register

# topic.topics[].topics[].label
TRCVIPCSSCTLR: Trace ViewInst Start/Stop PE Comparator Control Register

# topic.topics[].topics[].label
TRCVISSCTLR: Trace ViewInst Start/Stop Control Register

# topic.topics[].topics[].label
TRCVMIDCCTLR0: Trace Virtual Context Identifier Comparator Control Register 0

# topic.topics[].topics[].label
TRCVMIDCCTLR1: Trace Virtual Context Identifier Comparator Control Register 1

# topic.topics[].topics[].label
TRCVMIDCVR<n>: Trace Virtual Context Identifier Comparator Value Register <n>

# topic.topics[].topics[].label
TRFCR_EL1: Trace Filter Control Register (EL1)

# topic.topics[].topics[].label
TRFCR_EL2: Trace Filter Control Register (EL2)

# topic.topics[].topics[].label
TTBR0_EL1: Translation Table Base Register 0 (EL1)

# topic.topics[].topics[].label
TTBR0_EL2: Translation Table Base Register 0 (EL2)

# topic.topics[].topics[].label
TTBR0_EL3: Translation Table Base Register 0 (EL3)

# topic.topics[].topics[].label
TTBR1_EL1: Translation Table Base Register 1 (EL1)

# topic.topics[].topics[].label
TTBR1_EL2: Translation Table Base Register 1 (EL2)

# topic.topics[].topics[].label
TTTBRP_EL1: TIndex Transition Table Base Register Privileged (EL1)

# topic.topics[].topics[].label
TTTBRP_EL2: TIndex Transition Table Base Register Privileged (EL2)

# topic.topics[].topics[].label
TTTBRP_EL3: TIndex Transition Table Base Register Privileged (EL3)

# topic.topics[].topics[].label
TTTBRU_EL1: TIndex Transition Table Base Register Unprivileged (EL1)

# topic.topics[].topics[].label
TTTBRU_EL2: TIndex Transition Table Base Register Unprivileged (EL2)

# topic.topics[].topics[].label
VBAR_EL1: Vector Base Address Register (EL1)

# topic.topics[].topics[].label
VBAR_EL2: Vector Base Address Register (EL2)

# topic.topics[].topics[].label
VBAR_EL3: Vector Base Address Register (EL3)

# topic.topics[].topics[].label
VDISR_EL2: Virtual Deferred Interrupt Status Register (EL2)

# topic.topics[].topics[].label
VDISR_EL3: Virtual Deferred Interrupt Status Register (EL3)

# topic.topics[].topics[].label
VMECID_A_EL2: Alternate MECID for EL1&0 stage 2 translation regime

# topic.topics[].topics[].label
VMECID_P_EL2: Primary MECID for EL1&0 stage 2 translation regime

# topic.topics[].topics[].label
VNCCR_EL2: Virtual Nested Context Control Register

# topic.topics[].topics[].label
VNCR_EL2: Virtual Nested Control Register

# topic.topics[].topics[].label
VPIDR_EL2: Virtualization Processor ID Register

# topic.topics[].topics[].label
VSESR_EL2: Virtual SError Exception Syndrome Register (EL2)

# topic.topics[].topics[].label
VSESR_EL3: Virtual SError Exception Syndrome Register (EL3)

# topic.topics[].topics[].label
VSTTBR_EL2: Virtualization Secure Translation Table Base Register

# topic.topics[].topics[].label
VTLBID<n>_EL2: Virtual TLBI Domain Registers

# topic.topics[].topics[].label
VTLBIDOS<n>_EL2: Virtual TLBI Domain Outer Shareable Registers

# topic.topics[].topics[].label
VTTBR_EL2: Virtualization Translation Table Base Register

# topic.topics[].topics[].label
ATS12NSOPR: Address Translate Stages 1 and 2 Non-secure Only PL1 Read

# topic.topics[].topics[].label
ATS12NSOPW: Address Translate Stages 1 and 2 Non-secure Only PL1 Write

# topic.topics[].topics[].label
ATS12NSOUR: Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read

# topic.topics[].topics[].label
ATS12NSOUW: Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write

# topic.topics[].topics[].label
ATS1CPR: Address Translate Stage 1 Current state PL1 Read

# topic.topics[].topics[].label
ATS1CPRP: Address Translate Stage 1 Current state PL1 Read PAN

# topic.topics[].topics[].label
ATS1CPW: Address Translate Stage 1 Current state PL1 Write

# topic.topics[].topics[].label
ATS1CPWP: Address Translate Stage 1 Current state PL1 Write PAN

# topic.topics[].topics[].label
ATS1CUR: Address Translate Stage 1 Current state Unprivileged Read

# topic.topics[].topics[].label
ATS1CUW: Address Translate Stage 1 Current state Unprivileged Write

# topic.topics[].topics[].label
ATS1HR: Address Translate Stage 1 Hyp mode Read

# topic.topics[].topics[].label
ATS1HW: Address Translate Stage 1 Hyp mode Write

# topic.topics[].topics[].label
BPIALLIS: Branch Predictor Invalidate All, Inner Shareable

# topic.topics[].topics[].label
BPIMVA: Branch Predictor Invalidate by VA

# topic.topics[].topics[].label
CFPRCTX: Control Flow Prediction Restriction by Context

# topic.topics[].topics[].label
COSPRCTX: Clear Other Speculative Prediction Restriction by Context

# topic.topics[].topics[].label
CP15DMB: Data Memory Barrier System instruction

# topic.topics[].topics[].label
CP15DSB: Data Synchronization Barrier System instruction

# topic.topics[].topics[].label
CPPRCTX: Cache Prefetch Prediction Restriction by Context

# topic.topics[].topics[].label
DCCIMVAC: Data Cache line Clean and Invalidate by VA to PoC

# topic.topics[].topics[].label
DCCISW: Data Cache line Clean and Invalidate by Set/Way

# topic.topics[].topics[].label
DCCMVAC: Data Cache line Clean by VA to PoC

# topic.topics[].topics[].label
DCCMVAU: Data Cache line Clean by VA to PoU

# topic.topics[].topics[].label
DCIMVAC: Data Cache line Invalidate by VA to PoC

# topic.topics[].topics[].label
DCISW: Data Cache line Invalidate by Set/Way

# topic.topics[].topics[].label
DTLBIASID: Data TLB Invalidate by ASID match

# topic.topics[].topics[].label
DVPRCTX: Data Value Prediction Restriction by Context

# topic.topics[].topics[].label
ICIALLU: Instruction Cache Invalidate All to PoU

# topic.topics[].topics[].label
ICIALLUIS: Instruction Cache Invalidate All to PoU, Inner Shareable

# topic.topics[].topics[].label
ICIMVAU: Instruction Cache line Invalidate by VA to PoU

# topic.topics[].topics[].label
ITLBIALL: Instruction TLB Invalidate All

# topic.topics[].topics[].label
ITLBIASID: Instruction TLB Invalidate by ASID match

# topic.topics[].topics[].label
ITLBIMVA: Instruction TLB Invalidate by VA

# topic.topics[].topics[].label
TLBIALLHIS: TLB Invalidate All, Hyp mode, Inner Shareable

# topic.topics[].topics[].label
TLBIALLIS: TLB Invalidate All, Inner Shareable

# topic.topics[].topics[].label
TLBIALLNSNH: TLB Invalidate All, Non-Secure Non-Hyp

# topic.topics[].topics[].label
TLBIALLNSNHIS: TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable

# topic.topics[].topics[].label
TLBIASIDIS: TLB Invalidate by ASID match, Inner Shareable

# topic.topics[].topics[].label
TLBIIPAS2: TLB Invalidate by Intermediate Physical Address, Stage 2

# topic.topics[].topics[].label
TLBIIPAS2IS: TLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable

# topic.topics[].topics[].label
TLBIIPAS2L: TLB Invalidate by Intermediate Physical Address, Stage 2, Last level

# topic.topics[].topics[].label
TLBIIPAS2LIS: TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable

# topic.topics[].topics[].label
TLBIMVAA: TLB Invalidate by VA, All ASID

# topic.topics[].topics[].label
TLBIMVAAIS: TLB Invalidate by VA, All ASID, Inner Shareable

# topic.topics[].topics[].label
TLBIMVAAL: TLB Invalidate by VA, All ASID, Last level

# topic.topics[].topics[].label
TLBIMVAALIS: TLB Invalidate by VA, All ASID, Last level, Inner Shareable

# topic.topics[].topics[].label
TLBIMVAH: TLB Invalidate by VA, Hyp mode

# topic.topics[].topics[].label
TLBIMVAHIS: TLB Invalidate by VA, Hyp mode, Inner Shareable

# topic.topics[].topics[].label
TLBIMVAIS: TLB Invalidate by VA, Inner Shareable

# topic.topics[].topics[].label
TLBIMVAL: TLB Invalidate by VA, Last level

# topic.topics[].topics[].label
TLBIMVALH: TLB Invalidate by VA, Last level, Hyp mode

# topic.topics[].topics[].label
TLBIMVALHIS: TLB Invalidate by VA, Last level, Hyp mode, Inner Shareable

# topic.topics[].topics[].label
TLBIMVALIS: TLB Invalidate by VA, Last level, Inner Shareable

# topic.topics[].topics[].label
AT S12E0R: Address Translate Stages 1 and 2 EL0 Read

# topic.topics[].topics[].label
AT S12E0W: Address Translate Stages 1 and 2 EL0 Write

# topic.topics[].topics[].label
AT S12E1R: Address Translate Stages 1 and 2 EL1 Read

# topic.topics[].topics[].label
AT S12E1W: Address Translate Stages 1 and 2 EL1 Write

# topic.topics[].topics[].label
AT S1E0R: Address Translate Stage 1 EL0 Read

# topic.topics[].topics[].label
AT S1E0W: Address Translate Stage 1 EL0 Write

# topic.topics[].topics[].label
AT S1E1A: Address Translate Stage 1 EL1 Without Permission checks

# topic.topics[].topics[].label
AT S1E1R: Address Translate Stage 1 EL1 Read

# topic.topics[].topics[].label
AT S1E1RP: Address Translate Stage 1 EL1 Read PAN

# topic.topics[].topics[].label
AT S1E1W: Address Translate Stage 1 EL1 Write

# topic.topics[].topics[].label
AT S1E1WP: Address Translate Stage 1 EL1 Write PAN

# topic.topics[].topics[].label
AT S1E2A: Address Translate Stage 1 EL2 Without Permission checks

# topic.topics[].topics[].label
AT S1E2R: Address Translate Stage 1 EL2 Read

# topic.topics[].topics[].label
AT S1E2W: Address Translate Stage 1 EL2 Write

# topic.topics[].topics[].label
AT S1E3A: Address Translate Stage 1 EL3 Without Permission checks

# topic.topics[].topics[].label
AT S1E3R: Address Translate Stage 1 EL3 Read

# topic.topics[].topics[].label
AT S1E3W: Address Translate Stage 1 EL3 Write

# topic.topics[].topics[].label
BRB IALL: Invalidate the Branch Record Buffer

# topic.topics[].topics[].label
BRB INJ: Branch Record Injection into the Branch Record Buffer

# topic.topics[].topics[].label
CFP RCTX: Control Flow Prediction Restriction by Context

# topic.topics[].topics[].label
COSP RCTX: Clear Other Speculative Prediction Restriction by Context

# topic.topics[].topics[].label
CPP RCTX: Cache Prefetch Prediction Restriction by Context

# topic.topics[].topics[].label
DC CGDSW: Clean of Data and Allocation Tags by Set/Way

# topic.topics[].topics[].label
DC CGDVAC: Clean of Data and Allocation Tags by VA to PoC

# topic.topics[].topics[].label
DC CGDVADP: Clean of Data and Allocation Tags by VA to PoDP

# topic.topics[].topics[].label
DC CGDVAOC: Clean of Data and Allocation Tags by VA to Outer Cache level

# topic.topics[].topics[].label
DC CGDVAP: Clean of Data and Allocation Tags by VA to PoP

# topic.topics[].topics[].label
DC CGSW: Clean of Allocation Tags by Set/Way

# topic.topics[].topics[].label
DC CGVAC: Clean of Allocation Tags by VA to PoC

# topic.topics[].topics[].label
DC CGVADP: Clean of Allocation Tags by VA to PoDP

# topic.topics[].topics[].label
DC CGVAP: Clean of Allocation Tags by VA to PoP

# topic.topics[].topics[].label
DC CIGDPAE: Clean and invalidate of data and allocation tags by PA to PoE

# topic.topics[].topics[].label
DC CIGDPAPA: Clean and Invalidate of Data and Allocation Tags by PA to PoPA

# topic.topics[].topics[].label
DC CIGDSW: Clean and Invalidate of Data and Allocation Tags by Set/Way

# topic.topics[].topics[].label
DC CIGDVAC: Clean and Invalidate of Data and Allocation Tags by VA to PoC

# topic.topics[].topics[].label
DC CIGDVAOC: Clean and Invalidate of Data and Allocation Tags by VA to Outer Cache level

# topic.topics[].topics[].label
DC CIGDVAPS: Clean and Invalidate of Data and Allocation Tags by VA to PoPS

# topic.topics[].topics[].label
DC CIGSW: Clean and Invalidate of Allocation Tags by Set/Way

# topic.topics[].topics[].label
DC CIGVAC: Clean and Invalidate of Allocation Tags by VA to PoC

# topic.topics[].topics[].label
DC CIPAE: Data or unified Cache line Clean and Invalidate by PA to PoE

# topic.topics[].topics[].label
DC CIPAPA: Data or unified Cache line Clean and Invalidate by PA to PoPA

# topic.topics[].topics[].label
DC CISW: Data or unified Cache line Clean and Invalidate by Set/Way

# topic.topics[].topics[].label
DC CIVAC: Data or unified Cache line Clean and Invalidate by VA to PoC

# topic.topics[].topics[].label
DC CIVAOC: Data or unified Cache line Clean and Invalidate by VA to Outer Cache level

# topic.topics[].topics[].label
DC CIVAPS: Clean and Invalidate of Data by VA to PoPS

# topic.topics[].topics[].label
DC CSW: Data or unified Cache line Clean by Set/Way

# topic.topics[].topics[].label
DC CVAC: Data or unified Cache line Clean by VA to PoC

# topic.topics[].topics[].label
DC CVADP: Data or unified Cache line Clean by VA to PoDP

# topic.topics[].topics[].label
DC CVAOC: Data or unified Cache line Clean by VA to Outer Cache level

# topic.topics[].topics[].label
DC CVAP: Data or unified Cache line Clean by VA to PoP

# topic.topics[].topics[].label
DC CVAU: Data or unified Cache line Clean by VA to PoU

# topic.topics[].topics[].label
DC GBVA: Data Cache set Allocation Tag block by VA

# topic.topics[].topics[].label
DC GVA: Data Cache set Allocation Tag by VA

# topic.topics[].topics[].label
DC GZVA: Data Cache set Allocation Tags and Zero by VA

# topic.topics[].topics[].label
DC IGDSW: Invalidate of Data and Allocation Tags by Set/Way

# topic.topics[].topics[].label
DC IGDVAC: Invalidate of Data and Allocation Tags by VA to PoC

# topic.topics[].topics[].label
DC IGSW: Invalidate of Allocation Tags by Set/Way

# topic.topics[].topics[].label
DC IGVAC: Invalidate of Allocation Tags by VA to PoC

# topic.topics[].topics[].label
DC ISW: Data or unified Cache line Invalidate by Set/Way

# topic.topics[].topics[].label
DC IVAC: Data or unified Cache line Invalidate by VA to PoC

# topic.topics[].topics[].label
DC ZGBVA: Data Cache Zero Allocation tag block by VA

# topic.topics[].topics[].label
DVP RCTX: Data Value Prediction Restriction by Context

# topic.topics[].topics[].label
GCSPOPCX: Guarded Control Stack Pop and Compare exception return record

# topic.topics[].topics[].label
GCSPOPX: Guarded Control Stack Pop exception return record

# topic.topics[].topics[].label
GCSPUSHX: Guarded Control Stack Push exception return record

# topic.topics[].topics[].label
GCSSS1: Guarded Control Stack Switch Stack 1

# topic.topics[].topics[].label
GCSSS2: Guarded Control Stack Switch Stack 2

# topic.topics[].topics[].label
GIC CDAFF: Interrupt Set Target in the Current Interrupt Domain

# topic.topics[].topics[].label
GIC CDDI: Interrupt Deactivate in the Current Interrupt Domain

# topic.topics[].topics[].label
GIC CDDIS: Interrupt Disable in the Current Interrupt Domain

# topic.topics[].topics[].label
GIC CDEN: Interrupt Enable in the Current Interrupt Domain

# topic.topics[].topics[].label
GIC CDEOI: Priority Drop in the Current Interrupt Domain

# topic.topics[].topics[].label
GIC CDHM: Interrupt Handling mode state in the Current Interrupt Domain

# topic.topics[].topics[].label
GIC CDPEND: Interrupt Set/Clear Pending state in the Current Interrupt Domain

# topic.topics[].topics[].label
GIC CDPRI: Interrupt Set priority in the Current Interrupt Domain

# topic.topics[].topics[].label
GIC CDRCFG: Request Interrupt Configuration in the Current Interrupt Domain

# topic.topics[].topics[].label
GIC LDAFF: Interrupt Set Target in the Logical Interrupt Domain

# topic.topics[].topics[].label
GIC LDDI: Interrupt Deactivate in the Logical Interrupt Domain

# topic.topics[].topics[].label
GIC LDDIS: Interrupt Disable in the Logical Interrupt Domain

# topic.topics[].topics[].label
GIC LDEN: Interrupt Enable in the Logical Interrupt Domain

# topic.topics[].topics[].label
GIC LDHM: Interrupt Handling mode in the Logical Interrupt Domain

# topic.topics[].topics[].label
GIC LDPEND: Interrupt Set/Clear Pending state in the Logical Interrupt Domain

# topic.topics[].topics[].label
GIC LDPRI: Interrupt Set priority in the Logical Interrupt Domain

# topic.topics[].topics[].label
GIC LDRCFG: Request Interrupt Configuration in the Logical Interrupt Domain

# topic.topics[].topics[].label
GIC VDAFF: Interrupt Set Target in the Virtual Interrupt Domain

# topic.topics[].topics[].label
GIC VDDI: Interrupt Deactivate in the Virtual Interrupt Domain

# topic.topics[].topics[].label
GIC VDDIS: Interrupt Disable in the Virtual Interrupt Domain

# topic.topics[].topics[].label
GIC VDEN: Interrupt Enable in the Virtual Interrupt Domain

# topic.topics[].topics[].label
GIC VDHM: Interrupt Handling mode in the Virtual Interrupt Domain

# topic.topics[].topics[].label
GIC VDPEND: Interrupt Set/Clear Pending state in the Virtual Interrupt Domain

# topic.topics[].topics[].label
GIC VDPRI: Interrupt Set priority in the Virtual Interrupt Domain

# topic.topics[].topics[].label
GIC VDRCFG: Request Interrupt Configuration in the Virtual Interrupt Domain

# topic.topics[].topics[].label
GICR CDIA: Interrupt Acknowledge in the Current Interrupt Domain

# topic.topics[].topics[].label
GICR CDNMIA: Non-maskable Interrupt Acknowledge in the Current Interrupt Domain

# topic.topics[].topics[].label
GSB ACK: GIC Synchronization Barrier Interrupt Acknowledge

# topic.topics[].topics[].label
GSB SYS: GIC Synchronization Barrier System

# topic.topics[].topics[].label
IC IALLU: Instruction Cache Invalidate All to PoU

# topic.topics[].topics[].label
IC IALLUIS: Instruction Cache Invalidate All to PoU, Inner Shareable

# topic.topics[].topics[].label
IC IVAU: Instruction Cache line Invalidate by VA to PoU

# topic.topics[].topics[].label
MLBI VPIDE1: MLB Invalidate by Virtual PARTID and VMID

# topic.topics[].topics[].label
MLBI VPMGE1: MLB Invalidate by Virtual PMG and VMID

# topic.topics[].topics[].label
PLBI ALLE1, PLBI ALLE1NXS: PLB Invalidate All, EL1

# topic.topics[].topics[].label
PLBI ALLE1IS, PLBI ALLE1ISNXS: PLB Invalidate All, EL1, Inner Shareable

# topic.topics[].topics[].label
PLBI ALLE1OS, PLBI ALLE1OSNXS: PLB Invalidate All, EL1, Outer Shareable

# topic.topics[].topics[].label
PLBI ALLE2, PLBI ALLE2NXS: PLB Invalidate All, EL2

# topic.topics[].topics[].label
PLBI ALLE2IS, PLBI ALLE2ISNXS: PLB Invalidate All, EL2, Inner Shareable

# topic.topics[].topics[].label
PLBI ALLE2OS, PLBI ALLE2OSNXS: PLB Invalidate All, EL2, Outer Shareable

# topic.topics[].topics[].label
PLBI ALLE3, PLBI ALLE3NXS: PLB Invalidate All, EL3

# topic.topics[].topics[].label
PLBI ALLE3IS, PLBI ALLE3ISNXS: PLB Invalidate All, EL3, Inner Shareable

# topic.topics[].topics[].label
PLBI ALLE3OS, PLBI ALLE3OSNXS: PLB Invalidate All, EL3, Outer Shareable

# topic.topics[].topics[].label
PLBI ASIDE1, PLBI ASIDE1NXS: PLB Invalidate by ASID, EL1

# topic.topics[].topics[].label
PLBI ASIDE1IS, PLBI ASIDE1ISNXS: PLB Invalidate by ASID, EL1, Inner Shareable

# topic.topics[].topics[].label
PLBI ASIDE1OS, PLBI ASIDE1OSNXS: PLB Invalidate by ASID, EL1, Outer Shareable

# topic.topics[].topics[].label
PLBI PERMAE1, PLBI PERMAE1NXS: PLB Invalidate by Indicies, All ASID, EL1

# topic.topics[].topics[].label
PLBI PERMAE1IS, PLBI PERMAE1ISNXS: PLB Invalidate by Indicies, All ASID, EL1, Inner Shareable

# topic.topics[].topics[].label
PLBI PERMAE1OS, PLBI PERMAE1OSNXS: PLB Invalidate by Indicies, All ASID, EL1, Outer Shareable

# topic.topics[].topics[].label
PLBI PERME1, PLBI PERME1NXS: PLB Invalidate by Indicies, EL1

# topic.topics[].topics[].label
PLBI PERME1IS, PLBI PERME1ISNXS: PLB Invalidate by Indicies, EL1, Inner Shareable

# topic.topics[].topics[].label
PLBI PERME1OS, PLBI PERME1OSNXS: PLB Invalidate by Indicies, EL1, Outer Shareable

# topic.topics[].topics[].label
PLBI PERME2, PLBI PERME2NXS: PLB Invalidate by Indicies, EL2

# topic.topics[].topics[].label
PLBI PERME2IS, PLBI PERME2ISNXS: PLB Invalidate by Indicies, EL2, Inner Shareable

# topic.topics[].topics[].label
PLBI PERME2OS, PLBI PERME2OSNXS: PLB Invalidate by Indicies, EL2, Outer Shareable

# topic.topics[].topics[].label
PLBI PERME3, PLBI PERME3NXS: PLB Invalidate by Indicies, EL3

# topic.topics[].topics[].label
PLBI PERME3IS, PLBI PERME3ISNXS: PLB Invalidate by Indicies, EL3, Inner Shareable

# topic.topics[].topics[].label
PLBI PERME3OS, PLBI PERME3OSNXS: PLB Invalidate by Indicies, EL3, Outer Shareable

# topic.topics[].topics[].label
PLBI VMALLE1, PLBI VMALLE1NXS: PLB Invalidate by VMID, All, EL1

# topic.topics[].topics[].label
PLBI VMALLE1IS, PLBI VMALLE1ISNXS: PLB Invalidate by VMID, All, EL1, Inner Shareable

# topic.topics[].topics[].label
PLBI VMALLE1OS, PLBI VMALLE1OSNXS: PLB Invalidate by VMID, All, EL1, Outer Shareable

# topic.topics[].topics[].label
SYS S1_<op1>_<Cn>_<Cm>_<op2>, SYSL S1_<op1>_<Cn>_<Cm>_<op2>, SYSP S1_<op1>_<Cn>_<Cm>_<op2>: IMPLEMENTATION DEFINED System instructions

# topic.topics[].topics[].label
TLBI ALLE1, TLBI ALLE1NXS: TLB Invalidate All, EL1

# topic.topics[].topics[].label
TLBI ALLE1IS, TLBI ALLE1ISNXS: TLB Invalidate All, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI ALLE1OS, TLBI ALLE1OSNXS: TLB Invalidate All, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI ALLE2, TLBI ALLE2NXS: TLB Invalidate All, EL2

# topic.topics[].topics[].label
TLBI ALLE2IS, TLBI ALLE2ISNXS: TLB Invalidate All, EL2, Inner Shareable

# topic.topics[].topics[].label
TLBI ALLE2OS, TLBI ALLE2OSNXS: TLB Invalidate All, EL2, Outer Shareable

# topic.topics[].topics[].label
TLBI ALLE3, TLBI ALLE3NXS: TLB Invalidate All, EL3

# topic.topics[].topics[].label
TLBI ALLE3IS, TLBI ALLE3ISNXS: TLB Invalidate All, EL3, Inner Shareable

# topic.topics[].topics[].label
TLBI ALLE3OS, TLBI ALLE3OSNXS: TLB Invalidate All, EL3, Outer Shareable

# topic.topics[].topics[].label
TLBI ASIDE1, TLBI ASIDE1NXS: TLB Invalidate by ASID, EL1

# topic.topics[].topics[].label
TLBI ASIDE1IS, TLBI ASIDE1ISNXS: TLB Invalidate by ASID, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI ASIDE1OS, TLBI ASIDE1OSNXS: TLB Invalidate by ASID, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI IPAS2E1, TLBI IPAS2E1NXS: TLB Invalidate by Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].label
TLBI IPAS2E1IS, TLBI IPAS2E1ISNXS: TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI IPAS2E1OS, TLBI IPAS2E1OSNXS: TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI IPAS2LE1, TLBI IPAS2LE1NXS: TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].label
TLBI IPAS2LE1IS, TLBI IPAS2LE1ISNXS: TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI IPAS2LE1OS, TLBI IPAS2LE1OSNXS: TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI PAALL: TLB Invalidate GPT Information by PA, All Entries, Local

# topic.topics[].topics[].label
TLBI PAALLOS: TLB Invalidate GPT Information by PA, All Entries, Outer Shareable

# topic.topics[].topics[].label
TLBI RIPAS2E1, TLBI RIPAS2E1NXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].label
TLBI RIPAS2E1IS, TLBI RIPAS2E1ISNXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI RIPAS2E1OS, TLBI RIPAS2E1OSNXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI RIPAS2LE1, TLBI RIPAS2LE1NXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].label
TLBI RIPAS2LE1IS, TLBI RIPAS2LE1ISNXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI RIPAS2LE1OS, TLBI RIPAS2LE1OSNXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI RPALOS: TLB Range Invalidate GPT Information by PA, Last level, Outer Shareable

# topic.topics[].topics[].label
TLBI RPAOS: TLB Range Invalidate GPT Information by PA, Outer Shareable

# topic.topics[].topics[].label
TLBI RVAAE1, TLBI RVAAE1NXS: TLB Range Invalidate by VA, All ASID, EL1

# topic.topics[].topics[].label
TLBI RVAAE1IS, TLBI RVAAE1ISNXS: TLB Range Invalidate by VA, All ASID, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI RVAAE1OS, TLBI RVAAE1OSNXS: TLB Range Invalidate by VA, All ASID, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI RVAALE1, TLBI RVAALE1NXS: TLB Range Invalidate by VA, All ASID, Last level, EL1

# topic.topics[].topics[].label
TLBI RVAALE1IS, TLBI RVAALE1ISNXS: TLB Range Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI RVAALE1OS, TLBI RVAALE1OSNXS: TLB Range Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI RVAE1, TLBI RVAE1NXS: TLB Range Invalidate by VA, EL1

# topic.topics[].topics[].label
TLBI RVAE1IS, TLBI RVAE1ISNXS: TLB Range Invalidate by VA, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI RVAE1OS, TLBI RVAE1OSNXS: TLB Range Invalidate by VA, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI RVAE2, TLBI RVAE2NXS: TLB Range Invalidate by VA, EL2

# topic.topics[].topics[].label
TLBI RVAE2IS, TLBI RVAE2ISNXS: TLB Range Invalidate by VA, EL2, Inner Shareable

# topic.topics[].topics[].label
TLBI RVAE2OS, TLBI RVAE2OSNXS: TLB Range Invalidate by VA, EL2, Outer Shareable

# topic.topics[].topics[].label
TLBI RVAE3, TLBI RVAE3NXS: TLB Range Invalidate by VA, EL3

# topic.topics[].topics[].label
TLBI RVAE3IS, TLBI RVAE3ISNXS: TLB Range Invalidate by VA, EL3, Inner Shareable

# topic.topics[].topics[].label
TLBI RVAE3OS, TLBI RVAE3OSNXS: TLB Range Invalidate by VA, EL3, Outer Shareable

# topic.topics[].topics[].label
TLBI RVALE1, TLBI RVALE1NXS: TLB Range Invalidate by VA, Last level, EL1

# topic.topics[].topics[].label
TLBI RVALE1IS, TLBI RVALE1ISNXS: TLB Range Invalidate by VA, Last level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI RVALE1OS, TLBI RVALE1OSNXS: TLB Range Invalidate by VA, Last level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI RVALE2, TLBI RVALE2NXS: TLB Range Invalidate by VA, Last level, EL2

# topic.topics[].topics[].label
TLBI RVALE2IS, TLBI RVALE2ISNXS: TLB Range Invalidate by VA, Last level, EL2, Inner Shareable

# topic.topics[].topics[].label
TLBI RVALE2OS, TLBI RVALE2OSNXS: TLB Range Invalidate by VA, Last level, EL2, Outer Shareable

# topic.topics[].topics[].label
TLBI RVALE3, TLBI RVALE3NXS: TLB Range Invalidate by VA, Last level, EL3

# topic.topics[].topics[].label
TLBI RVALE3IS, TLBI RVALE3ISNXS: TLB Range Invalidate by VA, Last level, EL3, Inner Shareable

# topic.topics[].topics[].label
TLBI RVALE3OS, TLBI RVALE3OSNXS: TLB Range Invalidate by VA, Last level, EL3, Outer Shareable

# topic.topics[].topics[].label
TLBI VAAE1, TLBI VAAE1NXS: TLB Invalidate by VA, All ASID, EL1

# topic.topics[].topics[].label
TLBI VAAE1IS, TLBI VAAE1ISNXS: TLB Invalidate by VA, All ASID, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI VAAE1OS, TLBI VAAE1OSNXS: TLB Invalidate by VA, All ASID, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI VAALE1, TLBI VAALE1NXS: TLB Invalidate by VA, All ASID, Last level, EL1

# topic.topics[].topics[].label
TLBI VAALE1IS, TLBI VAALE1ISNXS: TLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI VAALE1OS, TLBI VAALE1OSNXS: TLB Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI VAE1, TLBI VAE1NXS: TLB Invalidate by VA, EL1

# topic.topics[].topics[].label
TLBI VAE1IS, TLBI VAE1ISNXS: TLB Invalidate by VA, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI VAE1OS, TLBI VAE1OSNXS: TLB Invalidate by VA, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI VAE2, TLBI VAE2NXS: TLB Invalidate by VA, EL2

# topic.topics[].topics[].label
TLBI VAE2IS, TLBI VAE2ISNXS: TLB Invalidate by VA, EL2, Inner Shareable

# topic.topics[].topics[].label
TLBI VAE2OS, TLBI VAE2OSNXS: TLB Invalidate by VA, EL2, Outer Shareable

# topic.topics[].topics[].label
TLBI VAE3, TLBI VAE3NXS: TLB Invalidate by VA, EL3

# topic.topics[].topics[].label
TLBI VAE3IS, TLBI VAE3ISNXS: TLB Invalidate by VA, EL3, Inner Shareable

# topic.topics[].topics[].label
TLBI VAE3OS, TLBI VAE3OSNXS: TLB Invalidate by VA, EL3, Outer Shareable

# topic.topics[].topics[].label
TLBI VALE1, TLBI VALE1NXS: TLB Invalidate by VA, Last level, EL1

# topic.topics[].topics[].label
TLBI VALE1IS, TLBI VALE1ISNXS: TLB Invalidate by VA, Last level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI VALE1OS, TLBI VALE1OSNXS: TLB Invalidate by VA, Last level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI VALE2, TLBI VALE2NXS: TLB Invalidate by VA, Last level, EL2

# topic.topics[].topics[].label
TLBI VALE2IS, TLBI VALE2ISNXS: TLB Invalidate by VA, Last level, EL2, Inner Shareable

# topic.topics[].topics[].label
TLBI VALE2OS, TLBI VALE2OSNXS: TLB Invalidate by VA, Last level, EL2, Outer Shareable

# topic.topics[].topics[].label
TLBI VALE3, TLBI VALE3NXS: TLB Invalidate by VA, Last level, EL3

# topic.topics[].topics[].label
TLBI VALE3IS, TLBI VALE3ISNXS: TLB Invalidate by VA, Last level, EL3, Inner Shareable

# topic.topics[].topics[].label
TLBI VALE3OS, TLBI VALE3OSNXS: TLB Invalidate by VA, Last level, EL3, Outer Shareable

# topic.topics[].topics[].label
TLBI VMALLE1, TLBI VMALLE1NXS: TLB Invalidate by VMID, All at stage 1, EL1

# topic.topics[].topics[].label
TLBI VMALLE1IS, TLBI VMALLE1ISNXS: TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI VMALLE1OS, TLBI VMALLE1OSNXS: TLB Invalidate by VMID, All at stage 1, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI VMALLS12E1, TLBI VMALLS12E1NXS: TLB Invalidate by VMID, All at Stage 1 and 2, EL1

# topic.topics[].topics[].label
TLBI VMALLS12E1IS, TLBI VMALLS12E1ISNXS: TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBI VMALLS12E1OS, TLBI VMALLS12E1OSNXS: TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBI VMALLWS2E1, TLBI VMALLWS2E1NXS: TLB Invalidate stage 2 dirty state by VMID, EL1&0

# topic.topics[].topics[].label
TLBI VMALLWS2E1IS, TLBI VMALLWS2E1ISNXS: TLB Invalidate stage 2 dirty state by VMID, EL1&0, Inner Shareable

# topic.topics[].topics[].label
TLBI VMALLWS2E1OS, TLBI VMALLWS2E1OSNXS: TLB Invalidate stage 2 write permission by VMID, EL1&0, Outer Shareable

# topic.topics[].topics[].label
TLBIP IPAS2E1, TLBIP IPAS2E1NXS: TLB Invalidate Pair by Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].label
TLBIP IPAS2E1IS, TLBIP IPAS2E1ISNXS: TLB Invalidate Pair by Intermediate Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP IPAS2E1OS, TLBIP IPAS2E1OSNXS: TLB Invalidate Pair by Intermediate Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP IPAS2LE1, TLBIP IPAS2LE1NXS: TLB Invalidate Pair by Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].label
TLBIP IPAS2LE1IS, TLBIP IPAS2LE1ISNXS: TLB Invalidate Pair by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP IPAS2LE1OS, TLBIP IPAS2LE1OSNXS: TLB Invalidate Pair by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP RIPAS2E1, TLBIP RIPAS2E1NXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].label
TLBIP RIPAS2E1IS, TLBIP RIPAS2E1ISNXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP RIPAS2E1OS, TLBIP RIPAS2E1OSNXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP RIPAS2LE1, TLBIP RIPAS2LE1NXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].label
TLBIP RIPAS2LE1IS, TLBIP RIPAS2LE1ISNXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP RIPAS2LE1OS, TLBIP RIPAS2LE1OSNXS: TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP RVAAE1, TLBIP RVAAE1NXS: TLB Range Invalidate by VA, All ASID, EL1

# topic.topics[].topics[].label
TLBIP RVAAE1IS, TLBIP RVAAE1ISNXS: TLB Range Invalidate by VA, All ASID, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP RVAAE1OS, TLBIP RVAAE1OSNXS: TLB Range Invalidate by VA, All ASID, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP RVAALE1, TLBIP RVAALE1NXS: TLB Range Invalidate by VA, All ASID, Last level, EL1

# topic.topics[].topics[].label
TLBIP RVAALE1IS, TLBIP RVAALE1ISNXS: TLB Range Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP RVAALE1OS, TLBIP RVAALE1OSNXS: TLB Range Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP RVAE1, TLBIP RVAE1NXS: TLB Range Invalidate by VA, EL1

# topic.topics[].topics[].label
TLBIP RVAE1IS, TLBIP RVAE1ISNXS: TLB Range Invalidate by VA, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP RVAE1OS, TLBIP RVAE1OSNXS: TLB Range Invalidate by VA, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP RVAE2, TLBIP RVAE2NXS: TLB Range Invalidate by VA, EL2

# topic.topics[].topics[].label
TLBIP RVAE2IS, TLBIP RVAE2ISNXS: TLB Range Invalidate by VA, EL2, Inner Shareable

# topic.topics[].topics[].label
TLBIP RVAE2OS, TLBIP RVAE2OSNXS: TLB Range Invalidate by VA, EL2, Outer Shareable

# topic.topics[].topics[].label
TLBIP RVAE3, TLBIP RVAE3NXS: TLB Range Invalidate by VA, EL3

# topic.topics[].topics[].label
TLBIP RVAE3IS, TLBIP RVAE3ISNXS: TLB Range Invalidate by VA, EL3, Inner Shareable

# topic.topics[].topics[].label
TLBIP RVAE3OS, TLBIP RVAE3OSNXS: TLB Range Invalidate by VA, EL3, Outer Shareable

# topic.topics[].topics[].label
TLBIP RVALE1, TLBIP RVALE1NXS: TLB Range Invalidate by VA, Last level, EL1

# topic.topics[].topics[].label
TLBIP RVALE1IS, TLBIP RVALE1ISNXS: TLB Range Invalidate by VA, Last level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP RVALE1OS, TLBIP RVALE1OSNXS: TLB Range Invalidate by VA, Last level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP RVALE2, TLBIP RVALE2NXS: TLB Range Invalidate by VA, Last level, EL2

# topic.topics[].topics[].label
TLBIP RVALE2IS, TLBIP RVALE2ISNXS: TLB Range Invalidate by VA, Last level, EL2, Inner Shareable

# topic.topics[].topics[].label
TLBIP RVALE2OS, TLBIP RVALE2OSNXS: TLB Range Invalidate by VA, Last level, EL2, Outer Shareable

# topic.topics[].topics[].label
TLBIP RVALE3, TLBIP RVALE3NXS: TLB Range Invalidate by VA, Last level, EL3

# topic.topics[].topics[].label
TLBIP RVALE3IS, TLBIP RVALE3ISNXS: TLB Range Invalidate by VA, Last level, EL3, Inner Shareable

# topic.topics[].topics[].label
TLBIP RVALE3OS, TLBIP RVALE3OSNXS: TLB Range Invalidate by VA, Last level, EL3, Outer Shareable

# topic.topics[].topics[].label
TLBIP VAAE1, TLBIP VAAE1NXS: TLB Invalidate Pair by VA, All ASID, EL1

# topic.topics[].topics[].label
TLBIP VAAE1IS, TLBIP VAAE1ISNXS: TLB Invalidate Pair by VA, All ASID, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP VAAE1OS, TLBIP VAAE1OSNXS: TLB Invalidate Pair by VA, All ASID, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP VAALE1, TLBIP VAALE1NXS: TLB Invalidate Pair by VA, All ASID, Last level, EL1

# topic.topics[].topics[].label
TLBIP VAALE1IS, TLBIP VAALE1ISNXS: TLB Invalidate Pair by VA, All ASID, Last Level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP VAALE1OS, TLBIP VAALE1OSNXS: TLB Invalidate Pair by VA, All ASID, Last Level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP VAE1, TLBIP VAE1NXS: TLB Invalidate Pair by VA, EL1

# topic.topics[].topics[].label
TLBIP VAE1IS, TLBIP VAE1ISNXS: TLB Invalidate Pair by VA, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP VAE1OS, TLBIP VAE1OSNXS: TLB Invalidate Pair by VA, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP VAE2, TLBIP VAE2NXS: TLB Invalidate Pair by VA, EL2

# topic.topics[].topics[].label
TLBIP VAE2IS, TLBIP VAE2ISNXS: TLB Invalidate Pair by VA, EL2, Inner Shareable

# topic.topics[].topics[].label
TLBIP VAE2OS, TLBIP VAE2OSNXS: TLB Invalidate Pair by VA, EL2, Outer Shareable

# topic.topics[].topics[].label
TLBIP VAE3, TLBIP VAE3NXS: TLB Invalidate Pair by VA, EL3

# topic.topics[].topics[].label
TLBIP VAE3IS, TLBIP VAE3ISNXS: TLB Invalidate Pair by VA, EL3, Inner Shareable

# topic.topics[].topics[].label
TLBIP VAE3OS, TLBIP VAE3OSNXS: TLB Invalidate Pair by VA, EL3, Outer Shareable

# topic.topics[].topics[].label
TLBIP VALE1, TLBIP VALE1NXS: TLB Invalidate Pair by VA, Last level, EL1

# topic.topics[].topics[].label
TLBIP VALE1IS, TLBIP VALE1ISNXS: TLB Invalidate Pair by VA, Last level, EL1, Inner Shareable

# topic.topics[].topics[].label
TLBIP VALE1OS, TLBIP VALE1OSNXS: TLB Invalidate Pair by VA, Last level, EL1, Outer Shareable

# topic.topics[].topics[].label
TLBIP VALE2, TLBIP VALE2NXS: TLB Invalidate Pair by VA, Last level, EL2

# topic.topics[].topics[].label
TLBIP VALE2IS, TLBIP VALE2ISNXS: TLB Invalidate Pair by VA, Last level, EL2, Inner Shareable

# topic.topics[].topics[].label
TLBIP VALE2OS, TLBIP VALE2OSNXS: TLB Invalidate Pair by VA, Last level, EL2, Outer Shareable

# topic.topics[].topics[].label
TLBIP VALE3, TLBIP VALE3NXS: TLB Invalidate Pair by VA, Last level, EL3

# topic.topics[].topics[].label
TLBIP VALE3IS, TLBIP VALE3ISNXS: TLB Invalidate Pair by VA, Last level, EL3, Inner Shareable

# topic.topics[].topics[].label
TLBIP VALE3OS, TLBIP VALE3OSNXS: TLB Invalidate Pair by VA, Last level, EL3, Outer Shareable

# topic.topics[].topics[].label
AMCFGR: Activity Monitors Configuration Register

# topic.topics[].topics[].label
AMCGCR: Activity Monitors Counter Group Configuration Register

# topic.topics[].topics[].label
AMCIDR0: Activity Monitors Component Identification Register 0

# topic.topics[].topics[].label
AMCIDR1: Activity Monitors Component Identification Register 1

# topic.topics[].topics[].label
AMCIDR2: Activity Monitors Component Identification Register 2

# topic.topics[].topics[].label
AMCIDR3: Activity Monitors Component Identification Register 3

# topic.topics[].topics[].label
AMCNTEN: Activity Monitors Count Set and Clear Register

# topic.topics[].topics[].label
AMCNTENCLR: Activity Monitors Count Enable Clear Register

# topic.topics[].topics[].label
AMCNTENCLR0: Activity Monitors Count Enable Clear Register 0

# topic.topics[].topics[].label
AMCNTENCLR1: Activity Monitors Count Enable Clear Register 1

# topic.topics[].topics[].label
AMCNTENSET: Activity Monitors Count Enable Set Register

# topic.topics[].topics[].label
AMCNTENSET0: Activity Monitors Count Enable Set Register 0

# topic.topics[].topics[].label
AMCNTENSET1: Activity Monitors Count Enable Set Register 1

# topic.topics[].topics[].label
AMCR: Activity Monitors Control Register

# topic.topics[].topics[].label
AMDEVAFF: Activity Monitors Device Affinity Register

# topic.topics[].topics[].label
AMDEVAFF0: Activity Monitors Device Affinity Register 0

# topic.topics[].topics[].label
AMDEVAFF1: Activity Monitors Device Affinity Register 1

# topic.topics[].topics[].label
AMDEVARCH: Activity Monitors Device Architecture Register

# topic.topics[].topics[].label
AMDEVTYPE: Activity Monitors Device Type Register

# topic.topics[].topics[].label
AMEVCNTR0<n>: Activity Monitors Event Counter Registers 0

# topic.topics[].topics[].label
AMEVCNTR1<n>: Activity Monitors Event Counter Registers 1

# topic.topics[].topics[].label
AMEVTYPER0<n>: Activity Monitors Event Type Registers 0

# topic.topics[].topics[].label
AMEVTYPER1<n>: Activity Monitors Event Type Registers 1

# topic.topics[].topics[].label
AMPIDR0: Activity Monitors Peripheral Identification Register 0

# topic.topics[].topics[].label
AMPIDR1: Activity Monitors Peripheral Identification Register 1

# topic.topics[].topics[].label
AMPIDR2: Activity Monitors Peripheral Identification Register 2

# topic.topics[].topics[].label
AMPIDR3: Activity Monitors Peripheral Identification Register 3

# topic.topics[].topics[].label
AMPIDR4: Activity Monitors Peripheral Identification Register 4

# topic.topics[].topics[].label
AMROOTCR: Activity Monitors Root Control Register

# topic.topics[].topics[].label
AMSCR: Activity Monitors Secure Control Register

# topic.topics[].topics[].label
ASICCTL: CTI External Multiplexer Control register

# topic.topics[].topics[].label
CNTEL0ACR: Counter-timer EL0 Access Control Register

# topic.topics[].topics[].label
CNTP_CTL: Counter-timer Physical Timer Control

# topic.topics[].topics[].label
CNTTIDR: Counter-timer Timer ID Register

# topic.topics[].topics[].label
CNTV_CTL: Counter-timer Virtual Timer Control

# topic.topics[].topics[].label
CTIAPPCLEAR: CTI Application Trigger Clear register

# topic.topics[].topics[].label
CTIAPPPULSE: CTI Application Pulse register

# topic.topics[].topics[].label
CTIAPPSET: CTI Application Trigger Set register

# topic.topics[].topics[].label
CTICHINSTATUS: CTI Channel In Status register

# topic.topics[].topics[].label
CTICHOUTSTATUS: CTI Channel Out Status register

# topic.topics[].topics[].label
CTICIDR0: CTI Component Identification Register 0

# topic.topics[].topics[].label
CTICIDR1: CTI Component Identification Register 1

# topic.topics[].topics[].label
CTICIDR2: CTI Component Identification Register 2

# topic.topics[].topics[].label
CTICIDR3: CTI Component Identification Register 3

# topic.topics[].topics[].label
CTICLAIMCLR: CTI CLAIM Tag Clear register

# topic.topics[].topics[].label
CTIDEVAFF0: CTI Device Affinity register 0

# topic.topics[].topics[].label
CTIDEVAFF1: CTI Device Affinity register 1

# topic.topics[].topics[].label
CTIDEVARCH: CTI Device Architecture register

# topic.topics[].topics[].label
CTIGATE: CTI Channel Gate Enable register

# topic.topics[].topics[].label
CTIINEN<n>: CTI Input Trigger to Output Channel Enable registers

# topic.topics[].topics[].label
CTIINTACK: CTI Output Trigger Acknowledge register

# topic.topics[].topics[].label
CTIITCTRL: CTI Integration mode Control register

# topic.topics[].topics[].label
CTIOUTEN<n>: CTI Input Channel to Output Trigger Enable registers

# topic.topics[].topics[].label
CTIPIDR0: CTI Peripheral Identification Register 0

# topic.topics[].topics[].label
CTIPIDR1: CTI Peripheral Identification Register 1

# topic.topics[].topics[].label
CTIPIDR2: CTI Peripheral Identification Register 2

# topic.topics[].topics[].label
CTIPIDR3: CTI Peripheral Identification Register 3

# topic.topics[].topics[].label
CTIPIDR4: CTI Peripheral Identification Register 4

# topic.topics[].topics[].label
CTITRIGINSTATUS: CTI Trigger In Status register

# topic.topics[].topics[].label
CTITRIGOUTSTATUS: CTI Trigger Out Status register

# topic.topics[].topics[].label
DBGBVR<n>_EL1: Debug Breakpoint Value Registers

# topic.topics[].topics[].label
DBGCLAIMCLR_EL1: Debug CLAIM Tag Clear Register

# topic.topics[].topics[].label
DBGCLAIMSET_EL1: Debug CLAIM Tag Set Register

# topic.topics[].topics[].label
DBGDTRRX_EL0: Debug Data Transfer Register, Receive

# topic.topics[].topics[].label
DBGDTRTX_EL0: Debug Data Transfer Register, Transmit

# topic.topics[].topics[].label
DBGWVR<n>_EL1: Debug Watchpoint Value Registers

# topic.topics[].topics[].label
EDAA32PFR: External Debug Auxiliary Processor Feature Register

# topic.topics[].topics[].label
EDACR: External Debug Auxiliary Control Register

# topic.topics[].topics[].label
EDCIDR0: External Debug Component Identification Register 0

# topic.topics[].topics[].label
EDCIDR1: External Debug Component Identification Register 1

# topic.topics[].topics[].label
EDCIDR2: External Debug Component Identification Register 2

# topic.topics[].topics[].label
EDCIDR3: External Debug Component Identification Register 3

# topic.topics[].topics[].label
EDCIDSR: External Debug Context ID Sample Register

# topic.topics[].topics[].label
EDDEVAFF0: External Debug Device Affinity register 0

# topic.topics[].topics[].label
EDDEVAFF1: External Debug Device Affinity register 1

# topic.topics[].topics[].label
EDDEVARCH: External Debug Device Architecture Register

# topic.topics[].topics[].label
EDDEVID: External Debug Device ID register 0

# topic.topics[].topics[].label
EDDEVID1: External Debug Device ID Register 1

# topic.topics[].topics[].label
EDDEVID2: External Debug Device ID register 2

# topic.topics[].topics[].label
EDDEVTYPE: External Debug Device Type register

# topic.topics[].topics[].label
EDDFR1: External Debug Feature Register 1

# topic.topics[].topics[].label
EDDFR2: External Debug Feature Register 2

# topic.topics[].topics[].label
EDECCR: External Debug Exception Catch Control Register

# topic.topics[].topics[].label
EDECR: External Debug Execution Control Register

# topic.topics[].topics[].label
EDESR: External Debug Event Status Register

# topic.topics[].topics[].label
EDHSR: External Debug Halting Syndrome Register

# topic.topics[].topics[].label
EDITCTRL: External Debug Integration mode Control register

# topic.topics[].topics[].label
EDITR: External Debug Instruction Transfer Register

# topic.topics[].topics[].label
EDLAR: External Debug Lock Access Register

# topic.topics[].topics[].label
EDLSR: External Debug Lock Status Register

# topic.topics[].topics[].label
EDPCSR: External Debug Program Counter Sample Register

# topic.topics[].topics[].label
EDPFR: External Debug Processor Feature Register

# topic.topics[].topics[].label
EDPIDR0: External Debug Peripheral Identification Register 0

# topic.topics[].topics[].label
EDPIDR1: External Debug Peripheral Identification Register 1

# topic.topics[].topics[].label
EDPIDR2: External Debug Peripheral Identification Register 2

# topic.topics[].topics[].label
EDPIDR3: External Debug Peripheral Identification Register 3

# topic.topics[].topics[].label
EDPIDR4: External Debug Peripheral Identification Register 4

# topic.topics[].topics[].label
EDPRCR: External Debug Power/Reset Control Register

# topic.topics[].topics[].label
EDPRSR: External Debug Processor Status Register

# topic.topics[].topics[].label
EDRCR: External Debug Reserve Control Register

# topic.topics[].topics[].label
EDSCR: External Debug Status and Control Register

# topic.topics[].topics[].label
EDSCR2: External Debug Status and Control Register 2

# topic.topics[].topics[].label
EDVIDSR: External Debug Virtual Context Sample Register

# topic.topics[].topics[].label
EDWAR: External Debug Watchpoint Address Register

# topic.topics[].topics[].label
ERR<n>ADDR: Error Record <n> Address Register

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ERR<n>CTLR: Error Record <n> Control Register

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ERR<n>FR: Error Record <n> Feature Register

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ERR<n>MISC0: Error Record <n> Miscellaneous Register 0

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ERR<n>MISC1: Error Record <n> Miscellaneous Register 1

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ERR<n>MISC2: Error Record <n> Miscellaneous Register 2

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ERR<n>MISC3: Error Record <n> Miscellaneous Register 3

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ERR<n>PFGCDN: Error Record <n> Pseudo-fault Generation Countdown Register

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ERR<n>PFGCTL: Error Record <n> Pseudo-fault Generation Control Register

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ERR<n>PFGF: Error Record <n> Pseudo-fault Generation Feature Register

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ERR<n>STATUS: Error Record <n> Primary Status Register

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ERRCIDR0: Component Identification Register 0

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ERRCIDR1: Component Identification Register 1

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ERRCIDR2: Component Identification Register 2

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ERRCIDR3: Component Identification Register 3

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ERRCRICR0: Critical Error Interrupt Configuration Register 0

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ERRCRICR1: Critical Error Interrupt Configuration Register 1

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ERRCRICR2: Critical Error Interrupt Configuration Register 2

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ERRERICR0: Error Recovery Interrupt Configuration Register 0

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ERRERICR1: Error Recovery Interrupt Configuration Register 1

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ERRERICR2: Error Recovery Interrupt Configuration Register 2

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ERRFHICR0: Fault Handling Interrupt Configuration Register 0

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ERRFHICR1: Fault Handling Interrupt Configuration Register 1

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ERRFHICR2: Fault Handling Interrupt Configuration Register 2

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ERRGSR<m>: Error Group <n> Status Register

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ERRIMPDEF<n>: IMPLEMENTATION DEFINED Register <n>

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ERRIRQCR<n>: Generic Error Interrupt Configuration Register <n>

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ERRIRQSR: Error Interrupt Status Register

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ERRPIDR0: Peripheral Identification Register 0

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ERRPIDR1: Peripheral Identification Register 1

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ERRPIDR2: Peripheral Identification Register 2

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ERRPIDR3: Peripheral Identification Register 3

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ERRPIDR4: Peripheral Identification Register 4

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GICC_ABPR: CPU Interface Aliased Binary Point Register

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GICC_AEOIR: CPU Interface Aliased End Of Interrupt Register

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GICC_AHPPIR: CPU Interface Aliased Highest Priority Pending Interrupt Register

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GICC_AIAR: CPU Interface Aliased Interrupt Acknowledge Register

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GICC_APR<n>: CPU Interface Active Priorities Registers

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GICC_BPR: CPU Interface Binary Point Register

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GICC_CTLR: CPU Interface Control Register

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GICC_DIR: CPU Interface Deactivate Interrupt Register

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GICC_EOIR: CPU Interface End Of Interrupt Register

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GICC_HPPIR: CPU Interface Highest Priority Pending Interrupt Register

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GICC_IAR: CPU Interface Interrupt Acknowledge Register

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GICC_IIDR: CPU Interface Identification Register

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GICC_NSAPR<n>: CPU Interface Non-secure Active Priorities Registers

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GICC_PMR: CPU Interface Priority Mask Register

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GICC_RPR: CPU Interface Running Priority Register

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GICC_STATUSR: CPU Interface Status Register

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GICD_CLRSPI_NSR: Clear Non-secure SPI Pending Register

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GICD_CLRSPI_SR: Clear Secure SPI Pending Register

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GICD_ICFGR<n>E: Interrupt Configuration Registers (Extended SPI Range)

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GICD_ICPENDR<n>E: Interrupt Clear-Pending Registers (extended SPI range)

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GICD_IGROUPR<n>E: Interrupt Group Registers (extended SPI range)

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GICD_IGRPMODR<n>E: Interrupt Group Modifier Registers (extended SPI range)

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GICD_INMIR<n>: Non-maskable Interrupt Registers, x = 0 to 31

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GICD_INMIR<n>E: Non-maskable Interrupt Registers for Extended SPIs, x = 0 to 31

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GICD_IPRIORITYR<n>E: Holds the priority of the corresponding interrupt for each extended SPI supported by the GIC.

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GICD_IROUTER<n>E: Interrupt Routing Registers (Extended SPI Range)

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GICD_ISACTIVER<n>E: Interrupt Set-Active Registers (extended SPI range)

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GICD_ISPENDR<n>E: Interrupt Set-Pending Registers (extended SPI range)

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GICD_SETSPI_NSR: Set Non-secure SPI Pending Register

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GICD_SETSPI_SR: Set Secure SPI Pending Register

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GICD_SGIR: Software Generated Interrupt Register

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GICD_STATUSR: Error Reporting Status Register

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GICD_TYPER: Interrupt Controller Type Register

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GICD_TYPER2: Interrupt Controller Type Register 2

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GICH_EISR: End Interrupt Status Register

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GICH_ELRSR: Empty List Register Status Register

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GICH_MISR: Maintenance Interrupt Status Register

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GICH_VMCR: Virtual Machine Control Register

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GICM_CLRSPI_NSR: Clear Non-secure SPI Pending Register

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GICM_CLRSPI_SR: Clear Secure SPI Pending Register

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GICM_SETSPI_NSR: Set Non-secure SPI Pending Register

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GICM_SETSPI_SR: Set Secure SPI Pending Register

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GICM_TYPER: Distributor MSI Type Register

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GICR_CLRLPIR: Clear LPI Pending Register

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GICR_ICFGR0: Interrupt Configuration Register 0

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GICR_ICFGR1: Interrupt Configuration Register 1

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GICR_IGROUPR0: Interrupt Group Register 0

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GICR_IGRPMODR0: Interrupt Group Modifier Register 0

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GICR_INMIR0: Non-maskable Interrupt Register 0

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GICR_INMIR<n>E: Non-maskable Interrupt Registers for Extended PPIs, x = 1 to 2.

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GICR_IPRIORITYR<n>E: Interrupt Priority Registers (extended PPI range)

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GICR_ISACTIVER0: Interrupt Set-Active Register 0

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GICR_ISENABLER0: Interrupt Set-Enable Register 0

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GICR_ISPENDR0: Interrupt Set-Pending Register 0

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GICR_MPAMIDR: Report maximum PARTID and PMG Register

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GICR_NSACR: Non-secure Access Control Register

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GICR_PARTIDR: Set PARTID and PMG Register

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GICR_PENDBASER: Redistributor LPI Pending Table Base Address Register

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GICR_STATUSR: Error Reporting Status Register

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GICR_VPENDBASER: Virtual Redistributor LPI Pending Table Base Address Register

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GICR_VPROPBASER: Virtual Redistributor Properties Base Address Register

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GICR_VSGIPENDR: Redistributor virtual SGI pending state register

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GICR_VSGIR: Redistributor virtual SGI pending state request register

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GICV_ABPR: Virtual Machine Aliased Binary Point Register

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GICV_AEOIR: Virtual Machine Aliased End Of Interrupt Register

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GICV_AHPPIR: Virtual Machine Aliased Highest Priority Pending Interrupt Register

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GICV_AIAR: Virtual Machine Aliased Interrupt Acknowledge Register

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GICV_APR<n>: Virtual Machine Active Priorities Registers

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GICV_BPR: Virtual Machine Binary Point Register

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GICV_CTLR: Virtual Machine Control Register

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GICV_DIR: Virtual Machine Deactivate Interrupt Register

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GICV_EOIR: Virtual Machine End Of Interrupt Register

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GICV_HPPIR: Virtual Machine Highest Priority Pending Interrupt Register

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GICV_IAR: Virtual Machine Interrupt Acknowledge Register

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GICV_IIDR: Virtual Machine CPU Interface Identification Register

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GICV_PMR: Virtual Machine Priority Mask Register

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GICV_RPR: Virtual Machine Running Priority Register

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GICV_STATUSR: Virtual Machine Error Reporting Status Register

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GITS_CBASER: ITS Command Queue Descriptor

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GITS_MPAMIDR: Report maximum PARTID and PMG Register

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GITS_PARTIDR: Set PARTID and PMG Register

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GITS_STATUSR: ITS Error Reporting Status Register

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MPAMCFG_CASSOC: MPAM Cache Maximum Associativity Partition Configuration Register

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MPAMCFG_CMAX: MPAM Cache Maximum Capacity Partition Configuration Register

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MPAMCFG_CMIN: MPAM Cache Minimum Capacity Partition Configuration Register

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MPAMCFG_CPBM<n>: MPAM Cache Portion Bitmap Partition Configuration Register

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MPAMCFG_DIS: MPAM Partition Configuration Disable Register

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MPAMCFG_EN: MPAM Partition Configuration Enable Register

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MPAMCFG_EN_FLAGS: MPAM Partition Configuration Enable Flags Register

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MPAMCFG_INTPARTID: MPAM Internal PARTID Narrowing Configuration Register

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MPAMCFG_IN_TL: MPAM Ingress PARTID Translation Configuration Register

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MPAMCFG_IN_TL_BASE: MPAM Ingress PARTID Translation Base Configuration Register

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MPAMCFG_IN_TL_MASK: MPAM Ingress PARTID Translation Mask Configuration Register

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MPAMCFG_MBW_MAX: MPAM Memory Bandwidth Maximum Partition Configuration Register

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MPAMCFG_MBW_MIN: MPAM Memory Bandwidth Minimum Partition Configuration Register

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MPAMCFG_MBW_PBM<n>: MPAM Bandwidth Portion Bitmap Partition Configuration Register

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MPAMCFG_MBW_PROP: MPAM Memory Bandwidth Proportional Stride Partition Configuration Register

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MPAMCFG_MBW_WINWD: MPAM Memory Bandwidth Partitioning Window Width Configuration Register

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MPAMCFG_OUT_TL: MPAM Egress PARTID Translation Configuration Register

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MPAMCFG_OUT_TL_BASE: MPAM Egress PARTID Translation Base Configuration Register

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MPAMCFG_OUT_TL_MASK: MPAM Egress PARTID Translation Mask Configuration Register

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MPAMCFG_PRI: MPAM Priority Partition Configuration Register

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MPAMF_CCAP_IDR: MPAM Features Cache Capacity Partitioning ID register

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MPAMF_CPOR_IDR: MPAM Features Cache Portion Partitioning ID register

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MPAMF_CSAMON_IDR: MPAM Features Cache Storage Allocation Monitoring ID register

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MPAMF_CSUMON_IDR: MPAM Features Cache Storage Usage Monitoring ID register

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MPAMF_ERR_MSI_ADDR_H: MPAM Error MSI High-part Address Register

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MPAMF_ERR_MSI_ADDR_L: MPAM Error MSI Low-part Address Register

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MPAMF_ERR_MSI_ATTR: MPAM Error MSI Write Attributes Register

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MPAMF_ERR_MSI_DATA: MPAM Error MSI Data Register

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MPAMF_ERR_MSI_MPAM: MPAM Error MSI Write MPAM Information Register

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MPAMF_IDR: MPAM Features Identification Register

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MPAMF_IN_TL_IDR: MPAM Ingress PARTID Translation ID Register

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MPAMF_MBWUMON_IDR: MPAM Features Memory Bandwidth Usage Monitoring ID register

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MPAMF_OUT_TL_IDR: MPAM Egress PARTID Translation ID Register

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MPAMF_PARTID_NRW_IDR: MPAM PARTID Narrowing ID register

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MPAMF_ROOTCR: MPAM Root Control Register

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MPAMF_SIDR: MPAM Features Secure Identification Register

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MSMON_CAPT_EVNT: MPAM Capture Event Generation Register

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MSMON_CFG_CSA_CTL: MPAM Memory System Monitor Configure Cache Storage Allocation Monitor Control Register

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MSMON_CFG_CSA_FLT: MPAM Memory System Monitor Configure Cache Storage Allocation Monitor Filter Register

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MSMON_CFG_CSU_CTL: MPAM Memory System Monitor Configure Cache Storage Usage Monitor Control Register

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MSMON_CFG_CSU_FLT: MPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter Register

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MSMON_CFG_MBWU_CTL: MPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control Register

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MSMON_CFG_MBWU_FLT: MPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter Register

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MSMON_CFG_MON_SEL: MPAM Monitor Instance Selection Register

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MSMON_CSA: MPAM Cache Storage Allocation Monitor Register

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MSMON_CSA_CAPTURE: MPAM Cache Storage Allocation Monitor Capture Register

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MSMON_CSA_L: MPAM Long Cache Storage Allocation Monitor Register

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MSMON_CSA_L_CAPTURE: MPAM Long Cache Storage Allocation Monitor Capture Register

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MSMON_CSA_OFSR: MPAM CSA Monitor Overflow Status Register

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MSMON_CSA_ROOTCR: MPAM Monitor Cache Storage Allocation Root Control Register

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MSMON_CSU: MPAM Cache Storage Usage Monitor Register

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MSMON_CSU_CAPTURE: MPAM Cache Storage Usage Monitor Capture Register

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MSMON_CSU_OFSR: MPAM CSU Monitor Overflow Status Register

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MSMON_CSU_ROOTCR: MPAM Monitor Cache Storage Usage Root Control Register

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MSMON_IN_TL: MPAM PMG Translation Ingress Control Register

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MSMON_IN_TL_BASE: MPAM PMG Translation Ingress Base Control Register

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MSMON_IN_TL_MASK: MPAM PMG Translation Ingress Mask Control Register

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MSMON_MBWU: MPAM Memory Bandwidth Usage Monitor Register

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MSMON_MBWU_CAPTURE: MPAM Memory Bandwidth Usage Monitor Capture Register

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MSMON_MBWU_L: MPAM Long Memory Bandwidth Usage Monitor Register

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MSMON_MBWU_L_CAPTURE: MPAM Long Memory Bandwidth Usage Monitor Capture Register

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MSMON_MBWU_OFSR: MPAM MBWU Monitor Overflow Status Register

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MSMON_MBWU_ROOTCR: MPAM Monitor Memory Bandwidth Usage Root Control Register

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MSMON_OFLOW_MSI_ADDR_H: MPAM Monitor Overflow MSI Write High-part Address Register

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MSMON_OFLOW_MSI_ADDR_L: MPAM Monitor Overflow MSI Low-part Address Register

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MSMON_OFLOW_MSI_ATTR: MPAM Monitor Overflow MSI Write Attributes Register

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MSMON_OFLOW_MSI_DATA: MPAM Monitor Overflow MSI Write Data Register

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MSMON_OFLOW_MSI_MPAM: MPAM Monitor Overflow MSI Write MPAM Information Register

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MSMON_OFLOW_SR: MPAM Monitor Overflow Status Register

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MSMON_OUT_TL: MPAM PMG Translation Egress Control Register

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MSMON_OUT_TL_BASE: MPAM PMG Translation Egress Base Control Register

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MSMON_OUT_TL_MASK: MPAM PMG Translation Egress Mask Control Register

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MSMON_PMG_SEL: MPAM PMG Selection Control Register

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MSMON_SEL_ROOTCR: MPAM Monitor Selection Root Control Register

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PMCCFILTR_EL0: Performance Monitors Cycle Counter Filter Register

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PMCCNTR_EL0: Performance Monitors Cycle Counter

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PMCCNTSVR_EL1: Performance Monitors Cycle Count Saved Value Register

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PMCCR: PMU Configuration Control Register

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PMCEID0: Performance Monitors Common Event Identification register 0

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PMCEID1: Performance Monitors Common Event Identification register 1

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PMCEID2: Performance Monitors Common Event Identification register 2

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PMCEID3: Performance Monitors Common Event Identification register 3

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PMCGCR0: Counter Group Configuration Register 0

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PMCIDR0: Performance Monitors Component Identification Register 0

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PMCIDR1: Performance Monitors Component Identification Register 1

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PMCIDR2: Performance Monitors Component Identification Register 2

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PMCIDR3: Performance Monitors Component Identification Register 3

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PMCNTEN: Performance Monitors Count Enable register

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PMCNTENCLR_EL0: Performance Monitors Count Enable Clear Register

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PMCNTENSET_EL0: Performance Monitors Count Enable Set Register

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PMCR_EL0: Performance Monitors Control Register

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PMDEVAFF: Performance Monitors Device Affinity register

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PMDEVAFF0: Performance Monitors Device Affinity register 0

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PMDEVAFF1: Performance Monitors Device Affinity register 1

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PMDEVARCH: Performance Monitors Device Architecture register

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PMDEVID: Performance Monitors Device ID register

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PMDEVTYPE: Performance Monitors Device Type register

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PMEVCNTR<n>_EL0: Performance Monitors Event Count Registers

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PMEVCNTSVR<n>_EL1: Performance Monitors Event Count Saved Value Registers

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PMEVFILT2R<n>: Performance Monitors Event Filter Registers

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PMEVTYPER<n>_EL0: Performance Monitors Event Type Registers

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PMICFILTR_EL0: Performance Monitors Instruction Counter Filter Register

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PMICNTSVR_EL1: Performance Monitors Instruction Count Saved Value Register

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PMINTEN: Performance Monitors Interrupt Enable register

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PMINTENCLR_EL1: Performance Monitors Interrupt Enable Clear Register

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PMINTENSET_EL1: Performance Monitors Interrupt Enable Set Register

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PMITCTRL: Performance Monitors Integration mode Control register

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PMLAR: Performance Monitors Lock Access Register

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PMLSR: Performance Monitors Lock Status Register

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PMMIR: Performance Monitors Machine Identification Register

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PMOVS: Performance Monitors Overflow Flag Status register

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PMOVSCLR_EL0: Performance Monitors Overflow Flag Status Clear register

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PMOVSSET_EL0: Performance Monitors Overflow Flag Status Set Register

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PMPCSCTL: PC Sample-based Profiling Control Register

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PMPIDR0: Performance Monitors Peripheral Identification Register 0

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PMPIDR1: Performance Monitors Peripheral Identification Register 1

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PMPIDR2: Performance Monitors Peripheral Identification Register 2

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PMPIDR3: Performance Monitors Peripheral Identification Register 3

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PMPIDR4: Performance Monitors Peripheral Identification Register 4

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PMSSCR_EL1: Performance Monitors Snapshot Status and Capture Register

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PMVCIDSR: CONTEXTIDR_EL1 and VMID Sample Register

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PMZR_EL0: Performance Monitors Zero with Mask

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TRBBASER_EL1: Trace Buffer Base Address Register

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TRBCIDR0: Component Identification Register 0

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TRBCIDR1: Component Identification Register 1

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TRBCIDR2: Component Identification Register 2

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TRBCIDR3: Component Identification Register 3

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TRBDEVARCH: Trace Buffer Device Architecture Register

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TRBDEVID1: Device Configuration Register 1

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TRBDEVID2: Device Configuration Register 2

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TRBITCTRL: Integration Mode Control Register

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TRBLIMITR_EL1: Trace Buffer Limit Address Register

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TRBMAR_EL1: Trace Buffer Memory Attribute Register

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TRBMPAM_EL1: Trace Buffer MPAM Configuration Register

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TRBPIDR0: Peripheral Identification Register 0

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TRBPIDR1: Peripheral Identification Register 1

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TRBPIDR2: Peripheral Identification Register 2

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TRBPIDR3: Peripheral Identification Register 3

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TRBPIDR4: Peripheral Identification Register 4

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TRBPIDR5: Peripheral Identification Register 5

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TRBPIDR6: Peripheral Identification Register 6

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TRBPIDR7: Peripheral Identification Register 7

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TRBPTR_EL1: Trace Buffer Write Pointer Register

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TRBSR_EL1: Trace Buffer Status/syndrome Register

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TRBTRG_EL1: Trace Buffer Trigger Counter Register

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TRCACATR<n>: Trace Address Comparator Access Type Register <n>

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TRCACVR<n>: Trace Address Comparator Value Register <n>

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TRCAUXCTLR: Trace Auxiliary Control Register

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TRCBBCTLR: Trace Branch Broadcast Control Register

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TRCCCCTLR: Trace Cycle Count Control Register

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TRCCIDCCTLR0: Trace Context Identifier Comparator Control Register 0

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TRCCIDCCTLR1: Trace Context Identifier Comparator Control Register 1

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TRCCIDCVR<n>: Trace Context Identifier Comparator Value Registers <n>

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TRCCIDR0: Trace Component Identification Register 0

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TRCCIDR1: Trace Component Identification Register 1

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TRCCIDR2: Trace Component Identification Register 2

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TRCCIDR3: Trace Component Identification Register 3

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TRCCLAIMCLR: Trace Claim Tag Clear Register

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TRCCLAIMSET: Trace Claim Tag Set Register

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TRCCNTCTLR<n>: Trace Counter Control Register <n>

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TRCCNTRLDVR<n>: Trace Counter Reload Value Register <n>

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TRCCNTVR<n>: Trace Counter Value Register <n>

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TRCDEVAFF: Trace Device Affinity Register

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TRCDEVARCH: Trace Device Architecture Register

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TRCDEVID: Trace Device Configuration Register

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TRCDEVID1: Trace Device Configuration Register 1

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TRCDEVID2: Trace Device Configuration Register 2

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TRCEVENTCTL0R: Trace Event Control 0 Register

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TRCEVENTCTL1R: Trace Event Control 1 Register

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TRCEXTINSELR<n>: Trace External Input Select Register <n>

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TRCIMSPEC<n>: Trace IMP DEF Register <n>

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TRCITCTRL: Trace Integration Mode Control Register

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TRCITEEDCR: Instrumentation Trace Extension External Debug Control Register

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TRCPDCR: Trace PowerDown Control Register

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TRCPDSR: Trace PowerDown Status Register

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TRCPIDR0: Trace Peripheral Identification Register 0

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TRCPIDR1: Trace Peripheral Identification Register 1

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TRCPIDR2: Trace Peripheral Identification Register 2

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TRCPIDR3: Trace Peripheral Identification Register 3

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TRCPIDR4: Trace Peripheral Identification Register 4

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TRCPIDR5: Trace Peripheral Identification Register 5

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TRCPIDR6: Trace Peripheral Identification Register 6

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TRCPIDR7: Trace Peripheral Identification Register 7

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TRCPRGCTLR: Trace Programming Control Register

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TRCQCTLR: Trace Q Element Control Register

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TRCRSCTLR<n>: Trace Resource Selection Control Register <n>

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TRCSEQEVR<n>: Trace Sequencer State Transition Control Register <n>

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TRCSEQRSTEVR: Trace Sequencer Reset Control Register

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TRCSEQSTR: Trace Sequencer State Register

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TRCSSCCR<n>: Trace Single-shot Comparator Control Register <n>

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TRCSSCSR<n>: Trace Single-shot Comparator Control Status Register <n>

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TRCSSPCICR<n>: Trace Single-shot Processing Element Comparator Input Control Register <n>

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TRCSTALLCTLR: Trace Stall Control Register

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TRCSYNCPR: Trace Synchronization Period Register

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TRCTSCTLR: Trace Timestamp Control Register

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TRCVICTLR: Trace ViewInst Main Control Register

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TRCVIIECTLR: Trace ViewInst Include/Exclude Control Register

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TRCVIPCSSCTLR: Trace ViewInst Start/Stop PE Comparator Control Register

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TRCVISSCTLR: Trace ViewInst Start/Stop Control Register

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TRCVMIDCCTLR0: Trace Virtual Context Identifier Comparator Control Register 0

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TRCVMIDCCTLR1: Trace Virtual Context Identifier Comparator Control Register 1

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TRCVMIDCVR<n>: Trace Virtual Context Identifier Comparator Value Register <n>

# metadata.contentDescription
This document provides descriptions in HTML format for the A-profile system registers and memory-mapped registers.