# title
Arm Zena Compute Subsystem Software Developer Guide

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Arm® Zena™ Compute Subsystem Software Developer Guide

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Debug port debug ROM with granular power requester

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Cluster Debug Block ROM (GPR ROM) ROM table

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I/O Block configuration space memory map

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RSE processor PPB and PPB Expansion RSE debug memory map

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RSE Main Interconnect Expansion interfaces memory map

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RSE integration layer expansion region memory map

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Register descriptions for the Primary Compute subsystem

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ATUMA_L, ATU Mismatched Address Low register

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ATUMA_H, ATU Mismatched Address High register

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ATURSSLA_L<n>, Least Significant Bits Of Right Shifted Start Logical Address n register, n = 0 - 31

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ATURSELA_L<n>, Least Significant (LS) Bits Of Right Shifted End Logical Address n register, n = 0 - 31

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ATURAV_L<n>, ATU Region Add Value Low n register, n = 0 - 31

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ATURAV_H<n>, ATU Region Add Value High n register, n = 0 - 31

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ATUROBA<n>, ATU Region Output Bus Attributes n register, n = 0 - 31

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ATURGPV<n>, ATU Region General Purpose n register, n = 0 - 31

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ATURSSLA_H<n>, Most Significant (MS) Bits Of Right Shifted Start Logical Address n register, n = 0 - 31

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ATURSELA_H<n>, Most Significant (MS) Bits Of Right Shifted End Logical Address n register, n = 0 - 31

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TRACECLK_CTRL, Trace Clock Control register

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DBG_APBCLK_CTRL, Debug APB Clock Control register

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CLK_FORCE_STATUS, Clock Force Status register

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CLK_FORCE_CLR, Clock Force Clear register

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DBG_PWR_REQ_ST, Debug Powerup Request Status register

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DBG_PWR_ACK, Debug Powerup Acknowledge register

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DBG_RST_REQ_ST, Debug Reset Request Status register

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DBG_RST_ACK, Debug Reset Acknowledge register

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PIK_CONFIG, Power Integration Kit Configuration register

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SID_PID_4, System ID Peripheral ID 4 register

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SID_PID_0, System ID Peripheral ID 0 register

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SID_PID_1, System ID Peripheral ID 1 register

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SID_PID_2, System ID Peripheral ID 2 register

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SID_PID_3, System ID Peripheral ID 3 register

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COMPID0, System ID Component ID 0 register

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COMPID1, System ID Component ID 1 register

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COMPID2, System ID Component ID 2 register

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COMPID3, System ID Component ID 3 register

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SMMU_PMU_IRPT, SMMU PMU Interrupt Status register

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SMMU_PMU_IRPT_CHK, SMMU PMU Interrupt Check Status register

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SMMU_RAS_LT_ERI, SMMU RAS Level-Triggered ERI Status register

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SMMU_RAS_LT_FHI_CHK, SMMU RAS Level-Triggered FHI Check Signal Status register

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SMMU_RAS_LT_FHI, SMMU RAS Level-Triggered FHI Status register

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SMMU_RAS_LT_ERI_CHK, SMMU RAS Level-Triggered ERI Check Signal status

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SMMU_RAS_LT_CRI, SMMU RAS Level-Triggered CRI Status register

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SMMU_RAS_LT_CRI_CHK, SMMU RAS Level-Triggered CRI Check Signal Status register

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IONI_PD_NS_INTERRUPTCHK, IONI Non-Secure Interrupt Check Status register

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IONI_NICLK_nPMUINTERRUPT, IONI Active-LOW PMU Interrupt Output Status register

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IONI_PD_INTERRUPTCHK, IONI Interrupt Check Status register

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TRI_REDT_INTR_O_IOBID_CFG, Triple-Redundancy PID0/1/2/3 and CID Interrupt Output Protection Status register

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SID_PID_4, System ID Peripheral ID 4 register

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SID_PID_0, System ID Peripheral ID 0 register

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SID_PID_1, System ID Peripheral ID 1 register

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SID_PID_2, System ID Peripheral ID 2 register

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SID_PID_3, System ID Peripheral ID 3 register

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COMPID0, System ID Component ID 0 register

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COMPID1, System ID Component ID 1 register

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COMPID2, System ID Component ID 2 register

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COMPID3, System ID Component ID 3 register

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RGM_CTRL, Reset Generation Manager Control register

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RGM_RST_SYNDROME, RGM Reset Syndrome register

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PIK_CONFIG, Power Integration Kit Configuration register

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SID_PID_4, System ID Peripheral ID 4 register

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SID_PID_0, System ID Peripheral ID 0 register

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SID_PID_1, System ID Peripheral ID 1 register

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SID_PID_2, System ID Peripheral ID 2 register

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SID_PID_3, System ID Peripheral ID 3 register

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COMPID0, System ID Component ID 0 register

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COMPID1, System ID Component ID 1 register

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COMPID2, System ID Component ID 2 register

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COMPID3, System ID Component ID 3 register

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IO_MMU_CFG, SMMU TBU Configuration register

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IO_TBU_NS_SID, SMMU TBU Non-secure SID Configuration register

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IO_TBU_S_SID, SMMU TBU Secure SID Configuration register

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IO_TCU_SID, Translation Control Unit (TCU) Stream ID register

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IO_TCU_SID_CHK, IO_TCU_SID Parity (chk) register

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SID_PID_4, System ID Peripheral ID 4 register

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SID_PID_0, System ID Peripheral ID 0 register

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SID_PID_1, System ID Peripheral ID 1 register

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SID_PID_2, System ID Peripheral ID 2 register

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SID_PID_3, System ID Peripheral ID 3 register

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COMPID0, System ID Component ID 0 register

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COMPID1, System ID Component ID 1 register

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COMPID2, System ID Component ID 2 register

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COMPID3, System ID Component ID 3 register

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CLX_CFG_ASTART0P0, Region 0 Port 0 Start Address Configuration register

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CLX_CFG_AEND0P0, Region 0 Port 0 End Address Configuration register

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CLX_CFG_ASTART1P0, Region 1 Port 0 Start Address Configuration register

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CLX_CFG_AEND1P0, Region 1 Port 0 End Address Configuration register

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CLX_CFG_ASTART2P0, Region 2 Port 0 Start Address Configuration register

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CLX_CFG_AEND2P0, Region 2 Port 0 End Address Configuration register

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CLX_CFG_ASTART3P0, Region 3 Port 0 Start Address Configuration register

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CLX_CFG_AEND3P0, Region 3 Port 0 End Address Configuration register

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CLX_CORE0_RVBARADDR_0, Core 0 Reset Vector Base Address Lower Configuration register

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CLX_CORE0_RVBARADDR_1, Core 0 Reset Vector Base Address Upper Configuration register

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CLX_CORE1_RVBARADDR_0, Core 1 Reset Vector Base Address Lower Configuration register

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CLX_CORE1_RVBARADDR_1, Core 1 Reset Vector Base Address Upper Configuration register

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CLX_CORE2_RVBARADDR_0, Core 2 Reset Vector Base Address Lower Configuration register

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CLX_CORE2_RVBARADDR_1, Core 2 Reset Vector Base Address Upper Configuration register

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CLX_CORE3_RVBARADDR_0, Core 3 Reset Vector Base Address Lower Configuration register

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CLX_CORE3_RVBARADDR_1, Core 3 Reset Vector Base Address Upper Configuration register

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CLX_CORE0_MPMMEN, Core 0 MPMM Configuration register

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CLX_CORE0_MPMMSTATE, Core 0 MPMM State register

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CLX_CORE1_MPMMEN, Core 1 MPMM Configuration register

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CLX_CORE1_MPMMSTATE, Core 1 MPMM State register

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CLX_CORE2_MPMMEN, Core 2 MPMM Configuration register

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CLX_CORE2_MPMMSTATE, Core 2 MPMM State register

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CLX_CORE3_MPMMEN, Core 3 MPMM Configuration register

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CLX_CORE3_MPMMSTATE, Core 3 MPMM State register

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CLX_CORE0_PDPSTATE, Core 0 PDP State Configuration register

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CLX_CORE1_PDPSTATE, Core 1 PDP State Configuration register

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CLX_CORE2_PDPSTATE, Core 2 PDP State Configuration register

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CLX_CORE3_PDPSTATE, Core 3 PDP State Configuration register

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CLX_CORE0_DISPBLK, Core 0 Dispatch Block Configuration register

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CLX_CORE1_DISPBLK, Core 1 Dispatch Block Configuration register

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CLX_CORE2_DISPBLK, Core 2 Dispatch Block Configuration register

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CLX_CORE3_DISPBLK, Core 3 Dispatch Block Configuration register

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CLX_CORE0_SW_WDT_CLR, Core 0 Watchdog Timer Clear register

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CLX_CORE1_SW_WDT_CLR, Core 1 Watchdog Timer Clear register

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CLX_CORE2_SW_WDT_CLR, Core 2 Watchdog Timer Clear register

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CLX_CORE3_SW_WDT_CLR, Core 3 Watchdog Timer Clear register

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CLX_PPU_IFP_FORCE, Cluster PPU Interface Protection Force register

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CLX_PPU_DCLS_CMPEN, Cluster PPU DCLS Compare Enable Configuration register

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CLX_PPU_DCLS_FORCE, PPU DCLS Force register

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CLX_CORE_DCLS_CMPENCP0, Core Pair 0 DCLS Compare Configuration register

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CLX_CORE_DCLS_FORCECP0, Force Core Pair 0 DCLS Control Signals register

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CLX_CORE_DCLS_CMPENCP1, Core Pair 0 DCLS Compare Configuration register

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CLX_CORE_DCLS_FORCECP1, Force Core Pair 1 DCLS Control Signals register

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CLX_CLUSTER_DCLS_FORCEP, Cluster Primary DCLS Force Bits Configuration register

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CLX_CLUSTER_DCLS_FORCER, Cluster Redundant DCLS Force Bits Configuration register

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CLX_PPU_IFP_FAULTP, PPU IFP Primary Fault Status Configuration register

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CLX_PPU_IFP_FAULTR, PPU IFP Redundant Fault Status Configuration register

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CLX_CLUSTER_IFP_FAULTP, Cluster IFP Primary Fault Indicators Configuration register

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CLX_PPU_DCLS_FAULTP, PPU DCLS Primary Fault Status register

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CLX_PPU_DCLS_FAULTR, PPU DCLS Redundant Fault Status register

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CLX_CORE_DCLS_FAULTCP0P, Core Pair 0 DCLS Primary Fault Configuration register

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CLX_CORE_DCLS_FAULTCP0R, Core Pair 0 DCLS Redundant Fault Configuration register

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CLX_CORE_DCLS_FAULTCP1P, Core Pair 1 DCLS Primary Fault Configuration register

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CLX_CORE_DCLS_FAULTCP1R, Core Pair 1 DCLS Redundant Fault Configuration register

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CLX_SBIST_BP_ERR, SBIST Bus Protection Error Status Configuration register

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CLX_SBIST_CORE0_TESTSTATUS, Core 0 SBIST Test Status register

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CLX_SBIST_CORE1_TESTSTATUS, Core 1 SBIST Test Status register

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CLX_SBIST_CORE2_TESTSTATUS, Core 2 SBIST Test Status register

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CLX_SBIST_CORE3_TESTSTATUS, Core 3 SBIST Test Status register

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CLX_SBIST_CORE0_TESTID, Core 0 SBIST Test ID register

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CLX_SBIST_CORE1_TESTID, Core 1 SBIST Test ID register.

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CLX_SBIST_CORE2_TESTID, Core 2 SBIST Test ID register

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CLX_SBIST_CORE3_TESTID, Core 3 SBIST Test ID register

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CLX_SBIST_CORE0_TESTFMODE, Core 0 SBIST Fault and Test Mode Status register

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CLX_SBIST_CORE1_TESTFMODE, Core 1 SBIST Fault and Test Mode Status register

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CLX_SBIST_CORE2_TESTFMODE, Core 2 SBIST Fault and Test Mode Status register

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CLX_SBIST_CORE3_TESTFMODE, Core 3 SBIST Fault and Test Mode Status register

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TRI_REDT_INTR, Triple Redundancy Error Interrupt register

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CLX_CORE0_PPUHWSTAT, Core 0 PPU Hardware Power Domain Status register

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CLX_CORE1_PPUHWSTAT, Core 1 PPU Hardware Power Domain Status register

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CLX_CORE2_PPUHWSTAT, Core 2 PPU Hardware Power Domain Status register

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CLX_CORE3_PPUHWSTAT, Core 3 PPU Hardware Power Domain Status register

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CLX_CLUSTER_PPUHWSTAT, Cluster PPU Hardware Power Domain Status register

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CLX_CORE_WDT_TIMEOUT, Core Watchdog Timeout Status register

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nCOREERRIRQ, Core Error Interrupt Outputs Latched Status register

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nCOREFAULTIRQ, Core Fault Interrupt Outputs Latched Status register

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CLK_DSU_PPU_nPMUINTERRUPT, DSU PPU Clock PMU Interrupt Status register

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CLK_PEB_nPMUINTERRUPT, PEB Clock PMU Interrupt Status register

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COMPID0, System ID Component ID 0 register

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COMPID1, System ID Component ID 1 register

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COMPID2, System ID Component ID 2 register

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COMPID3, System ID Component ID 3 register

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GCNT_TIMEOUT, Generic Counter Timeout register

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SLVCHIP_GCNT_UPDT_VAL_L, Secondary Generic Counter Update Lower Value register

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SLVCHIP_GCNT_UPDT_VAL_U, Secondary Generic Counter Update Upper Value register

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SLVCHIP_GCNT_NW_DLY, Secondary Generic Counter Network Delay register

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SLVCHIP_GCNT_RETRY_CNT, Secondary Generic Counter Retry Count register

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SLVCHIP_GCNT_MSTSLV_DIFF_L, Secondary Generic Counter Time value difference (Lower 32 bits)

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SECCHIP_GCNT_MSTSLV_DIFF_U, Secondary Generic Counter Time value difference (Upper 32 bits)

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EXP_UPDT_TIME_THRESHOLD, Expected Update Time Difference Threshold Value register

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MSTCHIP_GCNT_EXP_UPDT_TIME, Primary Generic Counter Expected Update Time register

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SLVCHIP_GCNT_EXP_UPDT_TIME, Secondary Generic Counter Expected Update Time register

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PID_4, Generic Counter Synchronization Peripheral ID 4 register

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PID_0, Generic Counter Synchronization Peripheral ID 0 register

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PID_1, Generic Counter Synchronization Peripheral ID 1 register

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PID_2, Generic Counter Synchronization Peripheral ID 2 register

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PID_3, Generic Counter Synchronization Peripheral ID 3 register

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COMP_ID0, Generic Counter Synchronization Component ID 0 register

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COMP_ID1, Generic Counter Synchronization Component ID 1 register

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COMP_ID2, Generic Counter Synchronization Component ID 2 register

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COMP_ID3, Generic Counter Synchronization Component ID 3 register

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SID_SYSTEM_ID, System ID System Identification register

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SID_SOC_ID, System ID SoC Identification register

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SID_CHIP_ID, System ID Chip Identification register

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SID_SYSTEM_CFG, System ID System Configuration register

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SID_PID_4, System ID Peripheral ID 4 register

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SID_PID_0, System ID Peripheral ID 0 register

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SID_PID_1, System ID Peripheral ID 1 register

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SID_PID_2, System ID Peripheral ID 2 register

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SID_PID_3, System ID Peripheral ID 3 register

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COMPID0, System ID Component ID 0 register

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COMPID1, System ID Component ID 1 register

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COMPID2, System ID Component ID 2 register

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COMPID3, System ID Component ID 3 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL0_0, Cluster 0 CORE CLK Control 0 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL0_1, Cluster 0 CORE CLK Control 1 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL0_2, Cluster 0 CORE CLK Control 2 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL0_3, Cluster 0 CORE CLK Control 3 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL1_0, Cluster 1 CORE CLK Control 0 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL1_1, Cluster 1 CORE CLK Control 1 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL1_2, Cluster 1 CORE CLK Control 2 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL1_3, Cluster 1 CORE CLK Control 3 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL2_0, Cluster 2 CORE CLK Control 0 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL2_1, Cluster 2 CORE CLK Control 1 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL2_2, Cluster 2 CORE CLK Control 2 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL2_3, Cluster 2 CORE CLK Control 3 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL3_0, Cluster 3 CORE CLK Control 0 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL3_1, Cluster 3 CORE CLK Control 1 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL3_2, Cluster 3 CORE CLK Control 2 register

# topic.topics[].topics[].topics[].topics[].label
CORE_CTRL3_3, Cluster 3 CORE CLK Control 3 register

# topic.topics[].topics[].topics[].topics[].label
DSU_PERIPHCLK_CTRL, DSU Clock PERIPHCLK Control register

# topic.topics[].topics[].topics[].topics[].label
DSU_ATCLK_CTRL, DSU Clock ATCLK Control register

# topic.topics[].topics[].topics[].topics[].label
DSU_GICCLK_CTRL, DSU Clock GICCLK Control register

# topic.topics[].topics[].topics[].topics[].label
DSU_PCLK_CTRL, DSU Clock PCLK Control register

# topic.topics[].topics[].topics[].topics[].label
DSU_PPUCLK_CTRL, DSU Clock PPUCLK Control register

# topic.topics[].topics[].topics[].topics[].label
PERIPHCLK_ACLK_CTRL, Peripheral Clock ACLK Control register

# topic.topics[].topics[].topics[].topics[].label
PERIPHCLK_PCLK_CTRL, Peripheral Clock PCLK Control register

# topic.topics[].topics[].topics[].topics[].label
GICCLK_CTRL, GIC Clock GICCLK Control register

# topic.topics[].topics[].topics[].topics[].label
IOCLK_CTRL, IO Block Clock IOCLK Control register

# topic.topics[].topics[].topics[].topics[].label
RSECLK_CTRL, RSE Clock RSECLK Control register

# topic.topics[].topics[].topics[].topics[].label
SISYSCLK_CTRL, SI System Clock SISYSCLK Control register

# topic.topics[].topics[].topics[].topics[].label
SICPU_CTRL, SI CPU Clock SICPUCLK Control register

# topic.topics[].topics[].topics[].topics[].label
SMDPERI_ACLK_CTRL, SMD Peripheral SMD PERI ACLK Control register

# topic.topics[].topics[].topics[].topics[].label
SMDPERI_PCLK_CTRL, SMD Peripheral SMD PERI PCLK Control register

# topic.topics[].topics[].topics[].topics[].label
CLKFORCE_STATUS, Clock Force Status register

# topic.topics[].topics[].topics[].topics[].label
CLKFORCE_CLR, Clock Force Clear register

# topic.topics[].topics[].topics[].topics[].label
SYS_PWR_REQ_ST, System Power-up Request Status register

# topic.topics[].topics[].topics[].topics[].label
SYS_RST_REQ_ST, System Reset Request Status register

# topic.topics[].topics[].topics[].topics[].label
SYS_RST_ACK, System Reset Request Acknowledge register

# topic.topics[].topics[].topics[].topics[].label
TRI_REDT_INTR, Triple Redundancy Interrupt Control and Status register

# topic.topics[].topics[].topics[].topics[].label
SID_PID_4, System ID Peripheral ID 4 register

# topic.topics[].topics[].topics[].topics[].label
SID_PID_0, System ID Peripheral ID 0 register

# topic.topics[].topics[].topics[].topics[].label
SID_PID_1, System ID Peripheral ID 1 register

# topic.topics[].topics[].topics[].topics[].label
SID_PID_2, System ID Peripheral ID 2 register

# topic.topics[].topics[].topics[].topics[].label
SID_PID_3, System ID Peripheral ID 3 register

# topic.topics[].topics[].topics[].topics[].label
COMPID0, System ID Component ID 0 register

# topic.topics[].topics[].topics[].topics[].label
COMPID1, System ID Component ID 1 register

# topic.topics[].topics[].topics[].topics[].label
COMPID2, System ID Component ID 2 register

# topic.topics[].topics[].topics[].topics[].label
COMPID3, System ID Component ID 3 register

# topic.topics[].topics[].topics[].label
RSE Secure Access Configuration register summary

# topic.topics[].topics[].topics[].topics[].label
SPCSECCTRL, Security Privilege Controller Security Configuration Control register

# topic.topics[].topics[].topics[].topics[].label
SECMPCINTSTAT, Secure MPC Interrupt Status

# topic.topics[].topics[].topics[].topics[].label
SECPPCINTSTAT, PPC Secure PPC Interrupt Status register

# topic.topics[].topics[].topics[].topics[].label
SECPPCINTCLR, PPC Secure PPC Interrupt Clear register

# topic.topics[].topics[].topics[].topics[].label
SECPPCINTEN, Secure PPC Interrupt Enable register

# topic.topics[].topics[].topics[].topics[].label
SECMSCINTSTAT, Secure MSC Interrupt Status register

# topic.topics[].topics[].topics[].topics[].label
SECMSCINTCLR, Secure MSC Interrupt Clear register

# topic.topics[].topics[].topics[].topics[].label
SECMSCINTEN, Secure MSC Interrupt Enable register

# topic.topics[].topics[].topics[].topics[].label
BRGINTSTAT, Bridge Buffer Error Interrupt Status register

# topic.topics[].topics[].topics[].topics[].label
BRGINTCLR, Bridge Buffer Error Interrupt Clear register

# topic.topics[].topics[].topics[].topics[].label
BRGINTEN, Bridge Buffer Error Interrupt Enable register

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPC0, Main Interconnect Non-secure Access Peripheral Protection Controller register

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPCEXP0 Main Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register 0

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPCEXP1 Main Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register 1

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPCEXP2 Main Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register 2

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPCEXP3 Main Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register 3

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPC0, Peripheral Interconnect Non-secure Access Peripheral Protection Controller register 0

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPC1, Peripheral Interconnect Non-secure Access Peripheral Protection Controller register 1

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPCEXP0, Peripheral Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register 0

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPCEXP1, Peripheral Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register 1

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPCEXP2, Peripheral Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register 2

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPCEXP3, Peripheral Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register 3

# topic.topics[].topics[].topics[].topics[].label
MAINSPPPC0, Secure Unprivileged Access Main Interconnect Subordinate Peripheral Protection Controller register

# topic.topics[].topics[].topics[].topics[].label
MAINSPPPCEXP0, Expansion Secure Privilege Access Main Interconnect Subordinate Peripheral Protection Controller register 0

# topic.topics[].topics[].topics[].topics[].label
MAINSPPPCEXP1, Expansion Secure Privilege Access Main Interconnect Subordinate Peripheral Protection Controller register 1

# topic.topics[].topics[].topics[].topics[].label
MAINSPPPCEXP2, Expansion Secure Privilege Access Main Interconnect Subordinate Peripheral Protection Controller register 2

# topic.topics[].topics[].topics[].topics[].label
MAINSPPPCEXP3, Expansion Secure Privilege Access Main Interconnect Subordinate Peripheral Protection Controller register 3

# topic.topics[].topics[].topics[].topics[].label
PERIPHSPPPC0, Secure Unprivileged Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 0

# topic.topics[].topics[].topics[].topics[].label
PERIPHSPPPC1, Secure Unprivileged Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 1

# topic.topics[].topics[].topics[].topics[].label
PERIPHSPPPCEXP0, Expansion Secure Privilege Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 0

# topic.topics[].topics[].topics[].topics[].label
PERIPHSPPPCEXP1, Expansion Secure Privilege Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 1

# topic.topics[].topics[].topics[].topics[].label
PERIPHSPPPCEXP2, Expansion Secure Privilege Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 2

# topic.topics[].topics[].topics[].topics[].label
PERIPHSPPPCEXP3, Expansion Secure Privilege Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 3

# topic.topics[].topics[].topics[].topics[].label
NSMSCEXP, Non-secure Expansion Manager Security Controller register

# topic.topics[].topics[].topics[].topics[].label
PIDR4, Secure Access Configuration Peripheral ID register 4

# topic.topics[].topics[].topics[].topics[].label
PIDR0, Secure Access Configuration Peripheral ID 0 register

# topic.topics[].topics[].topics[].topics[].label
PIDR1, Secure Access Configuration Peripheral ID 1 register

# topic.topics[].topics[].topics[].topics[].label
PIDR2, Secure Access Configuration Peripheral ID 02 register

# topic.topics[].topics[].topics[].topics[].label
PIDR3, Secure Access Configuration Peripheral ID 03 register

# topic.topics[].topics[].topics[].topics[].label
CIDR0, Secure Access Configuration Component ID 0 register

# topic.topics[].topics[].topics[].topics[].label
CIDR1, Secure Access Configuration Component ID 1 register

# topic.topics[].topics[].topics[].topics[].label
CIDR2, Secure Access Configuration Component ID 2 register

# topic.topics[].topics[].topics[].topics[].label
CIDR3, Secure Access Configuration Component ID 3 register

# topic.topics[].topics[].topics[].label
RSE Non-secure Access Configuration register summary

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPPC0, Non-secure Unprivileged Access Main Interconnect Subordinate PPC register 0

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPPCEXP0, Expansion Non-secure Privilege Access Main Interconnect Subordinate Peripheral Protection Controller register 0

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPPCEXP1, Expansion Non-secure Privilege Access Main Interconnect Subordinate Peripheral Protection Controller register 1

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPPCEXP2, Expansion Non-secure Privilege Access Main Interconnect Subordinate Peripheral Protection Controller register 2

# topic.topics[].topics[].topics[].topics[].label
MAINNSPPPCEXP3, Expansion Non-secure Privilege Access Main Interconnect Subordinate Peripheral Protection Controller register 3

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPPC0, Non-secure Unprivileged Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 0

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPPC1, Non-secure Unprivileged Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 1

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPPCEXP0, Expansion Non-secure Privilege Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 0

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPPCEXP1, Expansion Non-secure Privilege Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 1

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPPCEXP2, Expansion Non-secure Privilege Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 2

# topic.topics[].topics[].topics[].topics[].label
PERIPHNSPPPCEXP3, Expansion Non-secure Privilege Access Peripheral Interconnect Subordinate Peripheral Protection Controller register 3

# topic.topics[].topics[].topics[].topics[].label
PIDR4, Non-secure Access Configuration Peripheral ID register 4

# topic.topics[].topics[].topics[].topics[].label
PIDR0, Non-secure Access Configuration Peripheral ID 0 register

# topic.topics[].topics[].topics[].topics[].label
PIDR1, Non-secure Access Configuration Peripheral ID 1 register

# topic.topics[].topics[].topics[].topics[].label
PIDR2, Non-secure Access Configuration Peripheral ID 02 register

# topic.topics[].topics[].topics[].topics[].label
PIDR3, Non-secure Access Configuration Peripheral ID 03 register

# topic.topics[].topics[].topics[].topics[].label
CIDR0, Non-secure Access Configuration Component ID 0 register

# topic.topics[].topics[].topics[].topics[].label
CIDR1, Non-secure Access Configuration Component ID 1 register

# topic.topics[].topics[].topics[].topics[].label
CIDR2, Non-secure Access Configuration Component ID 2 register

# topic.topics[].topics[].topics[].topics[].label
CIDR3, Non-secure Access Configuration Component ID 3 register

# topic.topics[].topics[].topics[].label
RSE Timestamp Watchdogs Generic Watchdog Control Frame register summary

# topic.topics[].topics[].topics[].label
RSE Timestamp Watchdogs Generic Watchdog Refresh Frame register summary

# topic.topics[].topics[].topics[].label
RSE Local System Counter register summary

# topic.topics[].topics[].topics[].topics[].label
RSE Local System Counter Control Base register summary

# topic.topics[].topics[].topics[].topics[].label
RSE Local System Counter Read Base Register summary

# topic.topics[].topics[].topics[].topics[].label
PIDR4, CPU0_IDENTITY Peripheral ID register 4

# topic.topics[].topics[].topics[].topics[].label
PIDR0, CPU0_IDENTITY Peripheral ID 0 register

# topic.topics[].topics[].topics[].topics[].label
PIDR1, CPU0_IDENTITY Peripheral ID 1 register

# topic.topics[].topics[].topics[].topics[].label
PIDR2, CPU0_IDENTITY Peripheral ID 2 register

# topic.topics[].topics[].topics[].topics[].label
PIDR3, CPU0_IDENTITY Peripheral ID 3 register

# topic.topics[].topics[].topics[].topics[].label
CIDR0, CPU0_IDENTITY Component ID 0 register

# topic.topics[].topics[].topics[].topics[].label
CIDR1, CPU0_IDENTITY Component ID 1 register

# topic.topics[].topics[].topics[].topics[].label
CIDR2, CPU0_IDENTITY Component ID 2 register

# topic.topics[].topics[].topics[].topics[].label
CIDR3, CPU0_IDENTITY Component ID 3 register

# topic.topics[].topics[].topics[].topics[].label
CPUSECCFG, the Processor Local Security Configuration register

# topic.topics[].topics[].topics[].topics[].label
PIDR4, CPU0 SECCTRL Peripheral ID register 4

# topic.topics[].topics[].topics[].topics[].label
PIDR0, CPU0 SECCTRL Peripheral ID 0 register

# topic.topics[].topics[].topics[].topics[].label
PIDR1, CPU0 SECCTRL Peripheral ID 1 register

# topic.topics[].topics[].topics[].topics[].label
PIDR2, CPU0 SECCTRL Peripheral ID 2 register

# topic.topics[].topics[].topics[].topics[].label
PIDR3, CPU0 SECCTRL Peripheral ID 3 register

# topic.topics[].topics[].topics[].topics[].label
CIDR0, CPU0 SECCTRL Component ID 0 register

# topic.topics[].topics[].topics[].topics[].label
CIDR1, CPU0 SECCTRL Component ID 1 register

# topic.topics[].topics[].topics[].topics[].label
CIDR2, CPU0 SECCTRL Component ID 2 register

# topic.topics[].topics[].topics[].topics[].label
CIDR3, CPU0 SECCTRL Component ID 3 register

# topic.topics[].topics[].topics[].topics[].label
SYS_CONFIG0, the System Hardware Configuration register 0

# topic.topics[].topics[].topics[].topics[].label
SYS_CONFIG1, the System Hardware Configuration register 1

# topic.topics[].topics[].topics[].topics[].label
SYS_CONFIG2, the System Hardware Configuration register 2

# topic.topics[].topics[].topics[].topics[].label
IIDR, RSE Implementation Identity register

# topic.topics[].topics[].topics[].topics[].label
PIDR4, System Information Peripheral ID register 4

# topic.topics[].topics[].topics[].topics[].label
PIDR0, System Information Peripheral ID 0 register

# topic.topics[].topics[].topics[].topics[].label
PIDR1, System Information Peripheral ID 1 register

# topic.topics[].topics[].topics[].topics[].label
PIDR2, System Information Peripheral ID 2 register

# topic.topics[].topics[].topics[].topics[].label
PIDR3, System Information Peripheral ID 3 register

# topic.topics[].topics[].topics[].topics[].label
CIDR0, System Information Component ID 0 register

# topic.topics[].topics[].topics[].topics[].label
CIDR1, System Information Component ID 1 register

# topic.topics[].topics[].topics[].topics[].label
CIDR2, System Information Component ID 2 register

# topic.topics[].topics[].topics[].topics[].label
CIDR3, System Information Component ID 3 register

# topic.topics[].topics[].topics[].topics[].label
SCSECCTRL, System Control Security Controls register

# topic.topics[].topics[].topics[].topics[].label
CLK_CFG0, Clock Configuration register 0

# topic.topics[].topics[].topics[].topics[].label
CLK_CFG1, Clock Configuration register 1

# topic.topics[].topics[].topics[].topics[].label
GRETREG, General Purpose Retention register

# topic.topics[].topics[].topics[].topics[].label
INITSVTOR0, CPU0 Initial Secure Reset Vector register

# topic.topics[].topics[].topics[].topics[].label
NMI_ENABLE, Enabling and Disabling Non-Maskable Interrupts register

# topic.topics[].topics[].topics[].topics[].label
PPUINTSTAT, the PPU Interrupt Status register

# topic.topics[].topics[].topics[].topics[].label
PWRCTRL, Power Configuration and Control register

# topic.topics[].topics[].topics[].topics[].label
GRETEXREG, General Purpose Retention Expansion register

# topic.topics[].topics[].topics[].topics[].label
DMA_BOOT_EN, DMA-350 Boot Enable Static Configuration register

# topic.topics[].topics[].topics[].topics[].label
DMA_BOOT_ADDR, the DMA-350 Boot Static Configuration register

# topic.topics[].topics[].topics[].topics[].label
LCM_DCU_FORCE_DISABLE, the LCM DCU Force Disable register

# topic.topics[].topics[].topics[].topics[].label
PIDR4, System Control Peripheral ID register 4

# topic.topics[].topics[].topics[].topics[].label
PIDR0, System Control Peripheral ID 0 register

# topic.topics[].topics[].topics[].topics[].label
PIDR1, System Control Peripheral ID 1 register

# topic.topics[].topics[].topics[].topics[].label
PIDR2, System Control Peripheral ID 2 register

# topic.topics[].topics[].topics[].topics[].label
PIDR3, System Control Peripheral ID 3 register

# topic.topics[].topics[].topics[].topics[].label
CIDR0, System Control Component ID 0 register

# topic.topics[].topics[].topics[].topics[].label
CIDR1, System Control Component ID 1 register

# topic.topics[].topics[].topics[].topics[].label
CIDR2, System Control Component ID 2 register

# topic.topics[].topics[].topics[].topics[].label
CIDR3, System Control Component ID 3 register

# topic.topics[].topics[].topics[].label
RSE Processor Private Peripheral Bus region

# topic.topics[].topics[].topics[].topics[].label
Integration layer Control Unit registers

# topic.topics[].topics[].topics[].topics[].label
RSE Integration layer System Control APB register block registers

# topic.topics[].topics[].topics[].topics[].topics[].label
RSECORECLK_CTRL, RSE CPU0 Clock Control register

# topic.topics[].topics[].topics[].topics[].topics[].label
RSECORECLK_DIV, RSE CPU0 Clock Divider register

# topic.topics[].topics[].topics[].topics[].topics[].label
RSE_INTEGRATION, RSE Integration layer register

# topic.topics[].topics[].topics[].topics[].topics[].label
PID0, RSE Integration layer Peripheral ID 0 register

# topic.topics[].topics[].topics[].topics[].topics[].label
PID1, RSE Integration layer Peripheral ID 1 register

# topic.topics[].topics[].topics[].topics[].topics[].label
PID2, RSE Integration layer Peripheral ID 2 register

# topic.topics[].topics[].topics[].topics[].topics[].label
PID3, RSE Integration layer Peripheral ID 3 register

# topic.topics[].topics[].topics[].topics[].topics[].label
PID4, RSE Integration layer Peripheral ID 4 register

# topic.topics[].topics[].topics[].topics[].topics[].label
COMPID0, RSE Integration layer Component ID 0 register

# topic.topics[].topics[].topics[].topics[].topics[].label
COMPID1, RSE Integration layer Component ID 1 register

# topic.topics[].topics[].topics[].topics[].topics[].label
COMPID2, RSE Integration layer Component ID 2 register

# topic.topics[].topics[].topics[].topics[].topics[].label
COMPID3, RSE Integration layer Component ID 3 register

# topic.topics[].topics[].topics[].topics[].label
Diagnostics Control and Status Unit registers

# topic.topics[].topics[].topics[].topics[].topics[].label
Warm reset Registers File Generic Control Registers

# topic.topics[].topics[].topics[].topics[].topics[].label
Warm reset Registers File Generic Status Registers

# topic.topics[].topics[].topics[].topics[].topics[].label
Warm reset Registers File Generic Notification Registers

# topic.topics[].topics[].topics[].topics[].topics[].label
Warm reset Registers File Generic DP Registers

# topic.topics[].topics[].topics[].topics[].label
Fault Management Unit ERR<n>CTLR register

# topic.topics[].topics[].topics[].topics[].label
Fault Management Unit ERR<n>STATUS register

# topic.topics[].topics[].topics[].topics[].label
Fault Management Unit ERRIMPDEF<n> register

# topic.topics[].topics[].topics[].topics[].label
Fault Management Unit ERRGSR_L{0–5} register

# topic.topics[].topics[].topics[].topics[].label
Fault Management Unit ERRGSR_H{0–5} register

# topic.topics[].topics[].topics[].topics[].label
Safety Status Unit STATUS_DETAIL register

# metadata.contentDescription
The Software Developer Guide describes the EAC release functionality of the Zena CSS.