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Arm Corstone SSE-320 Example Subsystem Software Programmers Guide

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Arm® Corstone™ SSE-320 Example Subsystem Software Programmers Guide

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Trusted Base System Architecture for Armv8-M

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Power domain hierarchy and bounded regions

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Controlling the PD_VMR<i> minimum power states

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Wake from HIBERNATION0 using the PWRSYSWAKE Q-Channel Device Interface

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Secure Access Configuration register block

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SPCSECCTRL, Security Privilege Controller Security Configuration Control register

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SECMPCINTSTAT, Interrupt Status for Expansion Memory Protection Controller register

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MAINNSPPCEXP<0 to 3>, Main Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register

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PERIPHNSPPC0 and PERIPHNSPPC1, Non-secure Unprivileged Access Peripheral Interconnect Subordinate Peripheral Protection Controller register

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NPUSPPORSL, NPU Secure access security level reset control register

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PERIPHNSPPCEXP<0 to 3>, Peripheral Interconnect Non-secure Access Subordinate Peripheral Protection Controller Expansion register

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MAINSPPPCEXP<0 to 3>, Expansion Secure Unprivileged Access Main Interconnect Subordinate Peripheral Protection Controller register

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NPUSPPORPL, NPU Secure access privilege level reset control register

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PERIPHSPPPCEXP<0 to 3>, Expansion Secure Unprivileged Access Peripheral Interconnect Subordinate Peripheral Protection Controller register

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NSMSCEXP, Non-secure Expansion Manager Security Controller register

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Non-secure Access Configuration register block

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MAINNSPPPCEXP<0 to 3>, Expansion Non-secure Unprivileged Access Main Interconnect Subordinate Peripheral Protection Controller register

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PERIPHNSPPPC0 and PERIPHNSPPPC1, Non-secure Unprivileged Access Peripheral Interconnect Subordinate Peripheral Protection Controller register

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NPUNSPORPL, NPU Non-secure access privilege level reset control registers

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CPUPWRCFG, CPU software control registers

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CPUSECCFG, CPU Local Security Configuration Register

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SYS_CONFIG0, SYS_CONFIG1 and SYS_CONFIG2, System Hardware Configuration registers

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IIDR, Subsystem Implementation Identity register

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SECDBGSTAT, SECDBGSET and SECDBGCLR, Secure Debug Configuration registers

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SCSECCTRL, System Control Security Control register

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GRETREG, General Purpose Retention Register

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PPUINTSTAT, PPU interrupt status register

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PDCM_PD_SYS_SENSE, Power Dependency Control Matrix System power domain Sensitivity register

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PDCM_PD_CPU0_SENSE, Power Dependency Control Matrix System Power domain Sensitivity register

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PDCM_PD_VMR<M>_SENSE, Power Dependency Control Matrix Volatile Memory Region power domain sensitivity register

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Cortex-M85 or Cortex-M55 TPIU-M registers

# metadata.contentDescription
This is the software programmers guide for the Arm SSE-320 Example Subsystem, built on the Cortex-M85 processor.