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Arm CoreLink MMU-720AE System Memory Management Unit Technical Reference Manual

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Arm® CoreLink™ MMU-720AE System Memory Management Unit Technical Reference Manual

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About the MMU-720AE System Memory Management Unit

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Functional description of MMU-720AE  Components

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TCU Queue and Table Walk/Distributed Virtual Memory interface

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DTI interconnect register slice interfaces

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SMMUv3 PMU register architectural options

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Main TLB direct indexing and main TLB direct partitioning

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Conversion between ACE-Lite and Armv8 attributes

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Subordinate interface memory type attribute handling

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Manager interface memory type attribute handling

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AXI USER bits that the SMMU TBU TBM defines

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Page Based Hardware Attribute (PBHA) in SMMUs

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TBU subordinate interface attribute handling

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Transactions that can result in a translation fault

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Transactions that cannot result in a translation fault

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TCU I/O and buffer configuration parameters

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Common ACE-Lite and LTI TBU configuration parameters

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ACE-Lite TBU register slice configuration parameters

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ACE-Lite TBU I/O configuration parameters

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Common TBU debug configuration parameters

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Control which Safety Mechanisms report errors to the FMU

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Realm Management Extension Register Principles

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TCU and TBU PMU identification registers summary

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TCU Reliability, Availability, and Serviceability registers summary

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TBU Reliability, Availability, and Serviceability registers summary

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TCU component and peripheral ID registers

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ITOP_PIU register for the TCU Programmer Interface Unit

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ITIN_PIU register for the TCU Programmer Interface Unit

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ITOP_TMU register for the TCU Translation Management Unit

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ITIN_TMU register for the TCU Translation Management Unit

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TBU component and peripheral ID registers

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TCU Message Signaled Interrupt interface signals

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DTI interconnect switch DN_Sn interface signals

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DTI interconnect switch UP_Sn interface signals 

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DTI interconnect switch DN_M interface signals 

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DTI interconnect switch UP_M interface signals 

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DTI interconnect sizer LPI_CG interface signals

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DTI interconnect sizer DN_S interface signals

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DTI interconnect sizer UP_S interface signals

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DTI interconnect sizer DN_M interface signals

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DTI interconnect sizer UP_M interface signals

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DTI interconnect register slice LPI_CG interface signals

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DTI interconnect register slice DN_S interface signals

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DTI interconnect register slice UP_S interface signals

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DTI interconnect register slice DN_M interface signals

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DTI interconnect register slice UP_M interface signals

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ADB full inverted duplication protection

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Invalidating TLBs and configuration caches

# metadata.contentDescription
This Technical Reference Manual is written for system designers, system integrators, and programmers who are designing or programming a System-on-Chip (SoC) that uses the Arm Neoverse MMU-720AE System Memory Management Unit.