# title
Arm Total Compute 2022 Reference Design Software Developer Guide

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Arm® Total Compute 2022 Reference Design Software Developer Guide

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Overview of Total Compute 2022 Reference Design

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Processor core power down considerations

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About Total Compute 2022 Reference Design FVP

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SID_SYSTEM_ID, System ID System Identification register

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SID_SOC_ID register, System ID SoC Identification register

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SID_NODE_ID, System ID Node Identification register

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SID_SYSTEM_CFG, System ID System Configuration register

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PID4, System ID Peripheral ID 4 register

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PID0, System ID Peripheral ID 0 register

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PID1, System ID Peripheral ID 1 register

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PID2, System ID Peripheral ID 2 register

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PID3, System ID Peripheral ID 3 register

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CH_ST_MSK, MHU Channel Status Masked register

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CH_MSK_ST, MHU Channel Mask Status register

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CH_MSK_SET, MHU Channel Mask Set register

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CH_MSK_CLR, MHU Channel Mask Clear register

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MHU_CFG, Message Handling Unit Configuration register

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RESP_CFG, MHU Response Configuration register

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ACCESS_REQUEST, MHU Access Request register

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INT_ST, MHU Sender Interrupt Status register

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INT_CLR, MHU Sender Interrupt Clear register

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INT_EN, MHU Sender Interrupt Enable register

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INT_ST, MHU Receiver Interrupt Status register

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INT_CLR, MHU Receiver Interrupt Clear register

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INT_EN, MHU Receiver Interrupt Enable register

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CHCOMB_INT_ST<0-3>, MHU Sender Channel Combined Interrupt Status 0-3 register

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CHCOMB_INT_ST<0-3>, MHU Receiver Channel Combined Interrupt Status 0-3 register

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IIDR, MHU Implementer Identification register

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AIDR, MHU Architecture Identification register

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CNTSCR, Control Counter Synchronization Control register

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CNTSVL, Control Synchronized Counter Value Lower Value register

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CNTSVU, Control Synchronized Counter Value Upper Value register

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PID4, Generic Timer Peripheral ID 4 register

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PID0, Generic Timer Peripheral ID 0 register

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PID1, Generic Timer Peripheral ID 1 register

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PID2, Generic Timer Peripheral ID 2 register

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PID3, Generic Timer Peripheral ID 3 register

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CID0, Generic Timer Component ID 0 register

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CID1, Generic Timer Component ID 1 register

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CID2, Generic Timer Component ID 2 register

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CID3, Generic Timer Component ID 3 register

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Core Manager and Power Control (CPU PIK) registers

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DBGCLK_CLKDIV, Debug Clock Divider Control register

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DBGCLK_CLKSEL, Debug Clock Select Control register

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SCLK_CLKDIV, Clock divider control register

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CORE<x>CLK and COMPLEX<x>CLK Configuration registers

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CLKFORCE_STATUS_CLUSTER, Cluster Clock Force Status register

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CLKFORCE_SET_CLUSTER, Cluster Clock Force Set register

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CLKFORCE_CLR_CLUSTER, Cluster Clock Force Clear register

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CLKFORCE_STATUS_CORE, Core Clock Force Status register

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CLKFORCE_SET_CORE, Core Clock Force Set register

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CLKFORCE_CLR_CORE, Core Clock Force Clear register

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CLKFORCE_STATUS_COMPLEX, Complex Clock Force Status register

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CLKFORCE_SET_COMPLEX, Complex Clock Force Set register

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CLKFORCE_CLR_COMPLEX, Complex Clock Force Clear register

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CAP3, Core Manager and Power Control Capability Definition 3 register

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CAP2, Core Manager and Power Control Capability Definition 2 register

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CAP1, Core Power Control Capability Definition 1 register

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CAP0, Core Manager and Power Control Capability Definition 0 register

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PWR_CTRL_CONFIG, Core Manager and Power Control Configuration register

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PID 4, Core Manager and Power Control Peripheral ID 4 register

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PID 5-7, Core Manager and Power Control Peripheral ID 5-7 registers

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PID 0, Core Manager and Power Control Peripheral ID 0 register

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PID 1, Core Manager and Power Control Peripheral ID 1 register

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PID 2, Core Manager and Power Control Peripheral ID 2 register

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PID 3, Core Manager and Power Control Peripheral ID 3 register

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CID0, Core Manager and Power Control Component ID 0 register

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CID1, Core Manager and Power Control Component ID 1 register

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CID2, Core Manager and Power Control Component ID 2 register

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CID3, Core Manager and Power Control Component ID 3 register

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System Power Integration Kit (System PIK) registers

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PPUCLK_CTRL, System PPU Clock Control register

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PPUCLK_DIV1, System PPU Clock Divider Control register

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INTCLK_CTRL, Cache Coherent Interconnect Clock Control register

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INTCLK_DIV1, Cache Coherent Interconnect Clock Divider Control register

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TCU<n>CLK_CTRL, TCU<n> Clock Control register

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TCU<n>CLK_DIV1, TCU<n> Clock Divider Control register

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GICCLK_DIV1, GIC Clock Divider Control register

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SYSPERCLK_CTRL, System Peripheral Clock Control register

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SYSPERCLK_DIV1, System Peripheral Clock Divider Control register

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PCLKSCP_CTRL, SCP APB Clock Control register

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PCLKSCP_DIV1, SCP APB Clock Divider Control register

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SCLK_DIV1, SCLK Clock Divider Control register

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NS_UARTCLK_CTRL, Non-secure UART Clock Control register

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S_UARTCLK_CTRL, Secure UART Clock Control register

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NS_UARTCLK_DIV1, Non-secure UART Clock Divider Control register

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S_UARTCLK_DIV1, Secure UART Clock Divider Control register

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CLKFORCE_STATUS, System PIK Clock Force Status register

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CLKFORCE_SET, System PIK Clock Force Set register

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CLKFORCE_CLR, System PIK Clock Force Clear register

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SYSTOP_RST_DLY, SYSTOP Reset Delay register

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PWR_CTRL_CONFIG, System PIK Power Control Logic Configuration register

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PID4, System PIK Peripheral ID 4 register

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PID5-7, System PIK Peripheral ID 5-7 register

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PID0, System PIK Peripheral ID 0 register

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PID1, System PIK Peripheral ID 1 register

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PID2, System PIK Peripheral ID 2 register

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PID3, System PIK Peripheral ID 3 register

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CID0, System PIK Component ID 0 register

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CID1, System PIK Component ID 1 register

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CID2, System PIK Component ID 2 register

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CID3, System PIK Component ID 3 register

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Debug Power Control Logic (Debug PIK) registers

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DBG_PWR_REQ_ST0-3, Debug Power Request Status 0-3 registers

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DBG_PWR_ACK0-3, Debug Power Acknowledge 0-3 registers

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DBG_RST_REQ_ST, Debug Reset Request Status register

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DBG_RST_ACK, Debug Reset Acknowledge register

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SYS_PWR_REQ_ST0-3, System Power Request Status 0-3 registers

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SYS_PWR_ACK0-3, System Power Acknowledge 0-3 registers

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SYS_RST_REQ_ST, System Reset Request Status register

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SYS_RST_ACK, System Reset Acknowledge register

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Debug Clock Control registers (TRACECLK_CTRL, DBGCLK_CTRL, PCLKDBG_CTRL)

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Debug Clock Divider Control registers (TRACECLK_DIV1, DBGCLK_DIV1, PCLKDBG_DIV1)

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CLKFORCE_STATUS, Debug Clock Force Status register

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CLKFORCE_SET, Debug Clock Force SET register

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CLKFORCE_CLR, Debug Clock Force Clear register

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Debug and System Power Request Init Status registers (DBG_PWR_REQ_INT_ST0-3, SYS_PWR_REQ_INT_ST0-3)

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Debug and System Reset Request Init Status registers (DBG_RST_REQ_INT_ST, SYS_RST_REQ_INT_ST)

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PWR_CTRL_CONFIG, Debug Power Control Logic Configuration register

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PID4, Debug Power Control Peripheral ID 4 register

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PID5-7, Debug Peripheral ID 5-7 register

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PID0, Debug Power Control Peripheral ID 0 register

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PID1, Debug Power Control Peripheral ID 1 register

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PID2, Debug Power Control Peripheral ID 2 register

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PID3, Debug Power Control Peripheral ID 3 register

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CID0, Debug Power Control Component ID 0 register

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CID1, Debug Power Control Component ID 1 register

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CID2, Debug Power Control Component ID 2 register

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CID3, Debug Power Control Component ID 3 register

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DEBUG_PPU, Debug PPU Configuration-dependent registers (PPU_IDR0 and PPU_IDR1)

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GPU Power Control Logic (GPU PIK) registers

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GPUCLK_DIV, GPU Clock Divider Control registers

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GPUCORECLK_CTRL, GPU Clock Control register

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GPUCORECLK_DIV, GPU Clock Divider Control registers

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GPUSTACKSCLK_CTRL, GPU Clock Control registers

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GPUSTACKSCLK_DIV, GPU Clock Divider Control registers

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CLKFORCE_STATUS, GPU Clock Force Status register

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CLKFORCE_SET, GPU Clock Force SET register

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CLKFORCE_CLR, GPU Clock Force Clear register

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PWR_CTRL_CONFIG, GPU Power Control Logic Configuration register

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SCP Power Control Logic (SCP PIK) registers

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WIC_CTRL, WIC based Deep Sleep Control register

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WIC_STATUS, WIC based Deep Sleep Status register

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CLKFORCE_STATUS, Clock Force Status register

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CLKFORCE_SET, SCP Clock Force SET register

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CLKFORCE_CLR, Clock Force Clear register

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PWR_CTRL_CONFIG, SCP Power Control Logic Configuration register

# metadata.contentDescription
This document provides a high-level overview of Total Compute 2022 Reference Design (RD-TC22), including the system architecture and the functional description.