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Arm CoreLink DMA-250 Controller Technical Reference Manual

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Arm® CoreLink™ DMA-250 Controller Technical Reference Manual

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Separate AHB5 ports for data and virtual channel context

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Halting and restarting the DMA with Cross Trigger Interface

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Step 3 Configuring the DMA Unit Level register

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Step 4 Configuring a DMA Channel command

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Configuring burst generation on the Data AHB5 interface

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DMASECCFG summary, DMA Unit Security Configuration Register Frame

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DMASECCTRL summary, DMA Unit Secure Control Register Frame

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DMANSECCTRL summary, DMA Unit Non-secure Control Register Frame

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DMAINFO summary, DMA Unit Information Register Frame

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DMACH<n> summary, DMA Channel Register Frame

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This is the Technical Reference Manual for the CoreLink Direct Memory Access 250 Controller.