# title
Arm MMU L1 System Memory Management Unit Technical Reference Manual

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Arm® MMU L1 System Memory Management Unit Technical Reference Manual

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Transactions that can cause a translation fault

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Transactions that do not cause a translation fault

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TCU Queue and Table Walk and Distributed Virtual Memory interface

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TCU tie-off signals and operating parameters

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DTI interconnect register slice interfaces

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Main TLB direct indexing and main TLB direct partitioning

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Conversion between AXI and Armv8 attributes

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Completer interface memory type attribute handling

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Requester interface memory type attribute handling

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AXI USER bits that MMU L1 TBU TBM and TCU QTW/DVM define

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Translation Control Unit I/O configuration parameters

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Translation Control Unit buffer configuration parameters

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Translation Control Unit debug configuration parameters

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Translation Buffer Unit configuration parameters

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Translation Buffer Unit buffer configuration parameters

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Translation Buffer Unit register slice configuration parameters

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Translation Buffer Unit I/O configuration parameters

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Translation Buffer Unit debug configuration parameters

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SMMUv3 Performance Monitor Counter Group registers

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TCU and TBU PMU identification register summary

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TCU Reliability, Availability, and Serviceability register summary

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TCU component and peripheral ID registers

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ITOP register for the TCU Programmer Interface Unit

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ITOP register for the TCU Translation Management Unit

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ITIN register for the TCU Translation Management Unit

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TBU Reliability, Availability, and Serviceability registers

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TBU_ERRSTATUS, TBU Error Record Primary Syndrome register

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TBU_ERRGEN, TBU Error Generation register

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TCU Message Signaled Interrupt interface signals

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TBU transaction completer interface, completer interface signals

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TBU transaction requester interface, requester interface signals

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TBU Embedded Logic Analyzer debug signals

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Software initialization examples for MMU L1

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Invalidate TLBs and configuration caches

# metadata.contentDescription
This MMU L1 document provides information about the MMU L1 functional behavior and its software programmable registers.