# title
Arm Neoverse CMN S3(AE) Coherent Mesh Network Technical Reference Manual

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Arm® Neoverse™ CMN S3(AE) Coherent Mesh Network Technical Reference Manual

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I/O Home Node with PCIe peer-to-peer optimization

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CML Symmetric Multiprocessor (SMP) support

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CML Hybrid SMP Fully Coherent Accelerator support

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Tunneling PCIe traffic through CML_SMP link

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Streaming PCIe write traffic through CML_SMP link

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Host side data encryption for CXL Type-3 HDM-H memory device

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Dedicated RN-I resources for AXI port traffic

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Topology considerations when using extra device ports

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DTM changes when using extra device ports

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RN entry to and exit from Snoop and DVM domains

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Node ID mapping for configurations with extra device ports

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Support for PrefetchTarget operations in RN SAM

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RN SAM compact HN tables for multichip configurations

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Local HN-F and CPAG hash index: shuttering from total hash index bits

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HN-F to SN-F memory striping in HN-F SAM

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RN SAM programming with power-of-two hashing

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RN SAM programming for Prefetch Target to a non-hash region

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CMN S3(AE) SAM programming for Hierarchical Hashing

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Programming sequence to enable CXL.mem regions inside HNSAM

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Multichip flat, 64B interleaving across 4 chips

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HN-F interleave across local or remote HN-Fs at cache line interleaving of 64 bytes: Interleaving accross HNs

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HN-F interleave across local or remote HN-F: 4K interleaving across chips and 128 bytes interleaving across HNs

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GIC communication over AXI4-Stream ports

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Rules for avoiding deadlocks in non-XY routing

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PCIe Requester and Completer restrictions and requirements

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Error Detection and Deferred Error values

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Error detection, signaling, and reporting

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Support for early completion of DVMOp requests

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Remote DVM Optimization based on VMID filtering

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Software-configurable error injection in MTSX

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SLC memory system components and configuration

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SBSX and MTSX Persist and Tagmatch tracker

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Non-clustered and clustered modes for SF RN-F tracking

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Configuring non-clustered RN-F tracking in HN-F SF

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Configuring clustered mode for SF tracking

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Identifying clusters and individual devices in clustered mode

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Error reporting and software-configured error injection

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Transaction handling in SLC memory system

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CMO and PCMO propagation from HN-F to SN-F or SBSX

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Memory System Performance Resource Partitioning and Monitoring

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HN-F class-based resource allocation and arbitration

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Request retry based on POCQ resource allocation

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RNSAM programming for 2P (2 NUMA) HTG and CPA functionality for HN-S systems

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RNSAM programming for 4P (4 NUMA) HTG and CPA functionality for HN-S systems

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Configuring non-clustered RN-F tracking in HN-S SF

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Performance Monitoring Unit system overview

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Secure debug and Physical Address Spaces

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PCIe read burst preservation through the interconnect

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RN-I and RN-D AxID-based target selection

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CMN buffer lifetime and recommended parameter settings

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Requested read bandwidth at RN-I bridges

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Read bandwidth on interconnect at SBSX bridges

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Total requested bandwidth at SBSX bridges

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Delays at SBSX bridges because of backpressure

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Read bandwidth on interconnect at HN-I bridges

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Total requested bandwidth at HN-I bridges

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Delays at HN-I bridges because of ordering requirements

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Delays at HN-I bridges because of backpressure

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Occupancy and lifetime measurement using PMU events

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Node configuration register address mapping

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Requirements of configuration register reads and writes

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Program the dual channel selection scheme

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Programming MTU tag address generation registers

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Discover and bring up a local CMN S3(AE) system

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Program CML system to enable CML_SMP communication

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Options when programming CCG auxiliary control and configuration control registers

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Assign LinkIDs to remote CML protocol links

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Program CML protocol link control registers

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Program CPA functionality in HN-F LDID-to-PHYSID LUT

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Program CPA functionality in CML_SMP CCG-RA

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Programming to enable PCIe write tunneling through CML_SMP link

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Programming to enable PCIe write streaming through CML_SMP link

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Program CMN S3(AE) CML system at runtime

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Establish protocol link up between CML gateway and remote CML link

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Link down protocol link between CML gateway and remote CML link

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Entry and exit protocol links from coherency domains and DVM domains

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Program CML system to enable CHI C2C communication

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Program CML system to enable CXL communication

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Programming optimization for DVMs and CPU events

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AXI and ACE-Lite Requester interface signals

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Calculating the SBSX and MTSX AWID signal widths

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SBSX and MTSX AWID Width: Tracker Disabled

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HN-I and HN-P AxID signal properties and encodings

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Conditions for tying off AXI and ACE-Lite requester interface pins

# metadata.contentDescription
This manual is for the Arm Neoverse CMN S3(AE) Coherent Mesh Network. The manual contains functional safety information about the product and the development process.