# title
Arm  C1-DynamIQ™ Shared Unit Technical Reference Manual

# topic.label
Arm® C1-DynamIQ™ Shared Unit Technical Reference Manual

# topic.topics[].topics[].label
C1-DynamIQ Shared Unit configuration options

# topic.topics[].topics[].label
Core, complex, SME2  unit, and processing element numbering

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Integration of the SME2  unit in the cluster

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Emulated memory retention mode (MEM_RET_EMU)

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Setting automatic L3 cache power portion control

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L3 RAM power control using PPU static transactions

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Calculating values for threshold registers

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Power states for the cluster RAM instances

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Rules governing cluster PPU mode transitions

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Power mode transition dependencies for a dual-core  complex

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Power and reset control with Power Policy Units

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Encodings for cluster power and operating modes

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External core and SME2 unit PPU registers

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Programming sequences for the cluster, core, and SME2  unit  

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Programming sequence to bring the cluster, cores, and SME2  unit from Off to On mode

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Programming sequence to bring the cluster, core, and SME2  unit from On to Off mode

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Programming sequence for an interrupt controller to control transitions between On and Off mode

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Explicit reset of cluster, cores, SME2  units, and debug recovery mode

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Core software initiated Warm reset of an individual core

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Core software initiated Cold or Warm reset of the cluster, excluding the PPUs

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Warm reset of the cluster, excluding the PPUs

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Cold reset of the whole cluster, including the PPUs, retaining cache contents for debug

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Reset of the cluster, excluding the PPUs, retaining the cache contents for debug

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Power mode dependencies between the core or SME2, and the cluster

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Core Full retention mode and static mode restrictions

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Minimum mode and dynamic mode restrictions

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Memory System Resource Partitioning and Monitoring control

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Cache slice and requester port selection

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Multiple CHI bus requester port configurations

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Configure CHI bus requester ports to use address target groups

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Hashing for CHI transaction distribution

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Mapping for address target groups to CHI bus requester ports

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CHI transaction routing with multiple requester ports

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Attributes of the CHI requester interface

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Multiple AXI bus manager port configurations

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Configure AXI bus manager ports to use address target groups

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Hashing for AXI transaction distribution

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Mapping for address target groups to AXI bus manager ports

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AXI transaction routing with multiple manager ports

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AXI 256-bit manager interface attributes

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Control the receiving of DVM snoop transactions

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AXI 64-bit peripheral port interface properties

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AXI 256-bit peripheral port interface properties

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AXI 256-bit peripheral port transactions

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CHI peripheral port interface properties

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Read and write capabilities and transaction ID encoding

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AXI privilege information for the AXI-configured peripheral port

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Error reporting and performance monitoring

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Core access to system component registers

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Cluster, core, and SME2  unit PPU register access

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AArch64 generic system control registers

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External cluster, core, and SME2 CTI registers

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Trace output from cores and DynamIQ cluster

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ROM table power request registers for cluster and cores

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AArch64 generic system control registers summary

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IMP_CLUSTERREVIDR_EL1, Cluster ECO ID Register

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IMP_CLUSTERBUSQOS_EL1, Cluster Bus QoS Control Register

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IMP_CLUSTERL3HIT_EL1, Cluster L3 Hit Counter Register

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IMP_CLUSTERL3MISS_EL1, Cluster L3 Miss Counter Register

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IMP_CLUSTERPPSTART_EL1, Cluster Peripheral Port Start Address Register

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IMP_CLUSTERPPEND_EL1, Cluster Peripheral Port End Address Register

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AArch64 performance monitors registers summary

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IMP_CLUSTERPMOVSSET_EL1, Performance Monitors Overflow Flag Status Set Register

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IMP_CLUSTERPMOVSCLR_EL1, Performance Monitors Overflow Flag Status Clear Register

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IMP_CLUSTERPMCEID0_EL1, Performance Monitors Common Event Identification Register 0

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IMP_CLUSTERPMCEID1_EL1, Performance Monitors Common Event Identification Register 1

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ERXFR_EL1, Selected Error Record Feature Register

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ERXCTLR_EL1, Selected Error Record Control Register

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ERXSTATUS_EL1, Selected Error Record Primary Status Register

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ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0

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ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1

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ERXMISC2_EL1, Selected Error Record Miscellaneous Register 2

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ERXMISC3_EL1, Selected Error Record Miscellaneous Register 3

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External cluster system control registers summary

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CLUSTERIDR, Cluster Main Revision Register

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CLUSTERPWRCTLR, Cluster Power Control Register

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CLUSTERL3DNTH0, Cluster L3 Downsize Threshold0 Register

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CLUSTERL3DNTH1, Cluster L3 Downsize Threshold1 Register

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CLUSTERL3UPTH0, Cluster L3 Upsize Threshold0 Register

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CLUSTERL3UPTH1, Cluster L3 Upsize Threshold1 Register

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CLUSTERBUSQOS, Cluster Bus QoS Control Register

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CLUSTERACTLR, Cluster Auxiliary Control Register

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CLUSTERECTLR, Cluster Extended Control Register

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CLUSTERCFR2, Cluster Configuration Register 2

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CLUSTERPPMCR, Cluster PPM Control Register

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CLUSTERMPMMCR, Cluster MPMM Control Register

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CLUSTERL3UPTH2, Cluster L3 Upsize Threshold2 Register

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MPAMF_IDR, MPAM Features Identification Register

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MPAMF_SIDR, MPAM Features Secure Identification Register

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MPAMF_CPOR_IDR, MPAM Features Cache Portion Partitioning ID register

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MPAMCFG_MBW_PROP_ns, MPAM Memory Bandwidth Proportional Stride Partition Configuration for Non-Secure PARTIDs

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MPAMCFG_MBW_PROP_s, MPAM Memory Bandwidth Proportional Stride Partition Configuration for Secure PARTIDs

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MPAMCFG_CPBM_ns, MPAM Cache Portion Bitmap Partition Configuration Register for Non-secure PARTIDs

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MPAMCFG_CPBM_s, MPAM Cache Portion Bitmap Partition Configuration Register for Secure PARTIDs

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CLUSTERRAS_ERR0FR, Error Record <n> Feature Register

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CLUSTERRAS_ERR0CTLR, Error Record <n> Control Register

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CLUSTERRAS_ERR0STATUS, Error Record <n> Primary Status Register

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CLUSTERRAS_ERR0MISC0, Error Record <n> Miscellaneous Register 0

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CLUSTERRAS_ERR0MISC1, Error Record <n> Miscellaneous Register 1

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CLUSTERRAS_ERR0MISC2, Error Record <n> Miscellaneous Register 2

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CLUSTERRAS_ERR0MISC3, Error Record <n> Miscellaneous Register 3

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CLUSTERRAS_ERR0PFGF, Error Record <n> Pseudo-fault Generation Feature Register

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CLUSTERRAS_ERR0PFGCTL, Error Record <n> Pseudo-fault Generation Control Register

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CLUSTERRAS_ERR0PFGCDN, Error Record <n> Pseudo-fault Generation Countdown Register

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CLUSTERRAS_ERRGSR, Error Group Status Register

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PPU_PMER, Power Mode Emulation Enable Register

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PPU_DISR, Device Interface Input Current Status Register

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PPU_MISR, Miscellaneous Input Current Status Register

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PPU_PTCR, Power Mode Transition Register

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PPU_AIMR, Additional Interrupt Mask Register

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PPU_AISR, Additional Interrupt Status Register

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PPU_IESR, Input Edge Sensitivity Register

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PPU_OPSR, Operating Mode Active Edge Sensitivity Register

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PPU_FUNRR, Functional Retention RAM Configuration Register

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PPU_FULRR, Full Retention RAM Configuration Register

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PPU_MEMRR, Memory Retention RAM Configuration Register

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PPU_DCDR0, Device Control Delay Configuration Register 0

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PPU_DCDR1, Device Control Delay Configuration Register 1

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PPU_PIDR4, PPU Peripheral Identification Register 4

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PPU_PIDR5, PPU Peripheral Identification Register 5

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PPU_PIDR6, PPU Peripheral Identification Register 6

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PPU_PIDR7, PPU Peripheral Identification Register 7

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PPU_PIDR0, PPU Peripheral Identification Register 0

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PPU_PIDR1, PPU Peripheral Identification Register 1

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PPU_PIDR2, PPU Peripheral Identification Register 2

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PPU_PIDR3, PPU Peripheral Identification Register 3

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PPU_CIDR0, PPU Component Identification Register 0

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PPU_CIDR1, PPU Component Identification Register 1

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PPU_CIDR2, PPU Component Identification Register 2

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PPU_CIDR3, PPU Component Identification Register 3

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CLUSTERAMU_AMEVCNTR0, Activity Monitors Event Counter Registers 0

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CLUSTERAMU_AMEVCNTR1, Activity Monitors Event Counter Registers 0

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CLUSTERAMU_AMEVCNTR2, Activity Monitors Event Counter Registers 0

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CLUSTERAMU_AMEVCNTR3, Activity Monitors Event Counter Registers 0

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CLUSTERAMU_AMEVCNTR4, Activity Monitors Event Counter Registers 0

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CLUSTERAMU_AMEVTYPER0, Activity Monitors Event Type Registers 0

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CLUSTERAMU_AMEVTYPER1, Activity Monitors Event Type Registers 0

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CLUSTERAMU_AMEVTYPER2, Activity Monitors Event Type Registers 0

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CLUSTERAMU_AMEVTYPER3, Activity Monitors Event Type Registers 0

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CLUSTERAMU_AMEVTYPER4, Activity Monitors Event Type Registers 0

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CLUSTERAMU_AMCNTENSET, Activity Monitors Count Enable Set Register 0

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CLUSTERAMU_AMCNTENCLR, Activity Monitors Count Enable Clear Register 0

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CLUSTERAMU_AMDEVAFF, Activity Monitors Device Affinity Register 0

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CLUSTERAMU_AMDEVID, Cluster Activity Monitors Device ID register

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CLUSTERAMU_AMDEVTYPE, Activity Monitors Device Type Register

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External cluster PPU control registers summary

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CLUSTERCTL_CLUSTERPPUACTLR, Cluster Split/Lock PPU Chicken bit register

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External core and CME unit PPU registers summary

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PPU_PMER, Power Mode Emulation Enable Register

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PPU_DISR, Device Interface Input Current Status Register

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PPU_MISR, Miscellaneous Input Current Status Register

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PPU_PTCR, Power Mode Transition Register

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PPU_AIMR, Additional Interrupt Mask Register

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PPU_AISR, Additional Interrupt Status Register

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PPU_IESR, Input Edge Sensitivity Register

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PPU_OPSR, Operating Mode Active Edge Sensitivity Register

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PPU_FUNRR, Functional Retention RAM Configuration Register

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PPU_FULRR, Full Retention RAM Configuration Register

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PPU_MEMRR, Memory Retention RAM Configuration Register

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PPU_DCDR0, Device Control Delay Configuration Register 0

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PPU_DCDR1, Device Control Delay Configuration Register 1

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PPU_PIDR4, PPU Peripheral Identification Register 4

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PPU_PIDR5, PPU Peripheral Identification Register 5

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PPU_PIDR6, PPU Peripheral Identification Register 6

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PPU_PIDR7, PPU Peripheral Identification Register 7

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PPU_PIDR0, PPU Peripheral Identification Register 0

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PPU_PIDR1, PPU Peripheral Identification Register 1

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PPU_PIDR2, PPU Peripheral Identification Register 2

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PPU_PIDR3, PPU Peripheral Identification Register 3

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PPU_CIDR0, PPU Component Identification Register 0

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PPU_CIDR1, PPU Component Identification Register 1

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PPU_CIDR2, PPU Component Identification Register 2

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PPU_CIDR3, PPU Component Identification Register 3

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Registers accessed over the Debug APB bus

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External cluster, core, and SME2 unit CTI registers summary

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CTIINTACK, CTI Output Trigger Acknowledge register

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CTIAPPSET, CTI Application Trigger Set register

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CTIAPPCLEAR, CTI Application Trigger Clear register

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CTIAPPPULSE, CTI Application Pulse register

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CTIINEN0, CTI Input Trigger to Output Channel Enable registers

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CTIINEN1, CTI Input Trigger to Output Channel Enable registers

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CTIINEN2, CTI Input Trigger to Output Channel Enable registers

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CTIINEN3, CTI Input Trigger to Output Channel Enable registers

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CTIINEN4, CTI Input Trigger to Output Channel Enable registers

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CTIINEN5, CTI Input Trigger to Output Channel Enable registers

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CTIINEN6, CTI Input Trigger to Output Channel Enable registers

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CTIINEN7, CTI Input Trigger to Output Channel Enable registers

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CTIINEN8, CTI Input Trigger to Output Channel Enable registers

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CTIINEN9, CTI Input Trigger to Output Channel Enable registers

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CTIOUTEN0, CTI Input Channel to Output Trigger Enable registers

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CTIOUTEN1, CTI Input Channel to Output Trigger Enable registers

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CTIOUTEN2, CTI Input Channel to Output Trigger Enable registers

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CTIOUTEN3, CTI Input Channel to Output Trigger Enable registers

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CTIOUTEN4, CTI Input Channel to Output Trigger Enable registers

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CTIOUTEN5, CTI Input Channel to Output Trigger Enable registers

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CTIOUTEN6, CTI Input Channel to Output Trigger Enable registers

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CTIOUTEN7, CTI Input Channel to Output Trigger Enable registers

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CTIOUTEN8, CTI Input Channel to Output Trigger Enable registers

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CTIOUTEN9, CTI Input Channel to Output Trigger Enable registers

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CTITRIGINSTATUS, CTI Trigger In Status register

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CTITRIGOUTSTATUS, CTI Trigger Out Status register

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CTICHINSTATUS, CTI Channel In Status register

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CTICHOUTSTATUS, CTI Channel Out Status register

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CTIGATE, CTI Channel Gate Enable register

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CTICLAIMCLR, CTI CLAIM Tag Clear register

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CTIDEVAFF0, CTI Device Affinity register 0

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CTIDEVAFF1, CTI Device Affinity register 1

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CTIDEVARCH, CTI Device Architecture register

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CTIPIDR4, CTI Peripheral Identification Register 4

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CTIPIDR0, CTI Peripheral Identification Register 0

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CTIPIDR1, CTI Peripheral Identification Register 1

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CTIPIDR2, CTI Peripheral Identification Register 2

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CTIPIDR3, CTI Peripheral Identification Register 3

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CTICIDR0, CTI Component Identification Register 0

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CTICIDR1, CTI Component Identification Register 1

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CTICIDR2, CTI Component Identification Register 2

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CTICIDR3, CTI Component Identification Register 3

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CLUSTERROM_ROMENTRY0, Cluster ROM table entry 0

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CLUSTERROM_ROMENTRY1, Cluster ROM table entry 1

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CLUSTERROM_ROMENTRY2, Cluster ROM table entry

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CLUSTERROM_ROMENTRY3, Cluster ROM table entry

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CLUSTERROM_ROMENTRY4, Cluster ROM table entry

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CLUSTERROM_ROMENTRY5, Cluster ROM table entry

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CLUSTERROM_ROMENTRY6, Cluster ROM table entry

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CLUSTERROM_ROMENTRY7, Cluster ROM table entry

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CLUSTERROM_ROMENTRY8, Cluster ROM table entry

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CLUSTERROM_ROMENTRY9, Cluster ROM table entry

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CLUSTERROM_ROMENTRY10, Cluster ROM table entry

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CLUSTERROM_ROMENTRY11, Cluster ROM table entry

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CLUSTERROM_ROMENTRY12, Cluster ROM table entry

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CLUSTERROM_ROMENTRY13, Cluster ROM table entry

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CLUSTERROM_ROMENTRY14, Cluster ROM table entry

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CLUSTERROM_ROMENTRY15, Cluster ROM table entry

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CLUSTERROM_ROMENTRY16, Cluster ROM table entry

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CLUSTERROM_ROMENTRY17, Cluster ROM table entry

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CLUSTERROM_DBGPCR0, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR1, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR2, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR3, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR4, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR5, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR6, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR7, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR8, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR9, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR10, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR11, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR12, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR13, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR14, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPCR15, Cluster ROM table Debug Power Control Register

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CLUSTERROM_DBGPSR0, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR1, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR2, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR3, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR4, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR5, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR6, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR7, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR8, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR9, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR10, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR11, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR12, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR13, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR14, Cluster ROM table Debug Power Status Register

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CLUSTERROM_DBGPSR15, Cluster ROM table Debug Power Status Register

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CLUSTERROM_PRIDR0, Cluster ROM table Power Request ID Register 0

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CLUSTERROM_AUTHSTATUS, Cluster ROM table Authentication Status Register

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CLUSTERROM_DEVARCH, Cluster ROM table Device Architecture Register

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CLUSTERROM_DEVID, Cluster ROM table Device Configuration Register

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CLUSTERROM_DEVTYPE, Cluster ROM table Device Type Register

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CLUSTERROM_PIDR4, Cluster ROM table Peripheral Identification Register 4

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CLUSTERROM_PIDR0, Cluster ROM table Peripheral Identification Register 0

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CLUSTERROM_PIDR1, Cluster ROM table Peripheral Identification Register 1

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CLUSTERROM_PIDR2, Cluster ROM table Peripheral Identification Register 2

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CLUSTERROM_PIDR3, Cluster ROM table Peripheral Identification Register 3

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CLUSTERROM_CIDR0, Cluster ROM table Component Identification Register 0

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CLUSTERROM_CIDR1, Cluster ROM table Component Identification Register 1

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CLUSTERROM_CIDR2, Cluster ROM table Component Identification Register 2

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CLUSTERROM_CIDR3, Cluster ROM table Component Identification Register 3

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DBROM_ROMENTRY0, DebugBlock ROM table Entry 0

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DBROM_ROMENTRY1, DebugBlock ROM table Entry

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DBROM_ROMENTRY2, DebugBlock ROM table Entry

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DBROM_ROMENTRY3, DebugBlock ROM table Entry

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DBROM_ROMENTRY4, DebugBlock ROM table Entry

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DBROM_ROMENTRY5, DebugBlock ROM table Entry

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DBROM_ROMENTRY6, DebugBlock ROM table Entry

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DBROM_ROMENTRY7, DebugBlock ROM table Entry

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DBROM_ROMENTRY8, DebugBlock ROM table Entry

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DBROM_ROMENTRY9, DebugBlock ROM table Entry

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DBROM_ROMENTRY10, DebugBlock ROM table Entry

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DBROM_ROMENTRY11, DebugBlock ROM table Entry

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DBROM_ROMENTRY12, DebugBlock ROM table Entry

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DBROM_ROMENTRY13, DebugBlock ROM table Entry

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DBROM_ROMENTRY14, DebugBlock ROM table Entry

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DBROM_ROMENTRY15, DebugBlock ROM table Entry

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DBROM_ROMENTRY16, DebugBlock ROM table Entry

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DBROM_ROMENTRY17, DebugBlock ROM table Entry

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DBROM_DBGPCR0, DebugBlock ROM table Debug Power Control Register 0

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DBROM_DBGPSR0, DebugBlock ROM table Debug Power Status Register 0

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DBROM_PRIDR0, DebugBlock ROM table Power Request ID Register 0

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DBROM_AUTHSTATUS, DebugBlock ROM table Authentication Status Register

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DBROM_DEVARCH, DebugBlock ROM table Device Architecture Register

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DBROM_DEVID, DebugBlock ROM table Device Configuration Register

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DBROM_DEVTYPE, DebugBlock ROM table Device Type Register

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DBROM_PIDR4, DebugBlock ROM table Peripheral Identification Register 4

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DBROM_PIDR0, DebugBlock ROM table Peripheral Identification Register 0

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DBROM_PIDR1, DebugBlock ROM table Peripheral Identification Register 1

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DBROM_PIDR2, DebugBlock ROM table Peripheral Identification Register 2

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DBROM_PIDR3, DebugBlock ROM table Peripheral Identification Register 3

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DBROM_CIDR0, DebugBlock ROM table Component Identification Register 0

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DBROM_CIDR1, DebugBlock ROM table Component Identification Register 1

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DBROM_CIDR2, DebugBlock ROM table Component Identification Register 2

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DBROM_CIDR3, DebugBlock ROM table Component Identification Register 3

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CLUSTERPMU_PMEVCNTR0, Cluster Performance Monitors Event Count Registers

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CLUSTERPMU_PMEVCNTR1, Cluster Performance Monitors Event Count Registers

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CLUSTERPMU_PMEVCNTR2, Cluster Performance Monitors Event Count Registers

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CLUSTERPMU_PMEVCNTR3, Cluster Performance Monitors Event Count Registers

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CLUSTERPMU_PMEVCNTR4, Cluster Performance Monitors Event Count Registers

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CLUSTERPMU_PMEVCNTR5, Cluster Performance Monitors Event Count Registers

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CLUSTERPMU_PMEVTYPER0, Cluster Performance Monitors Event Type Registers

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CLUSTERPMU_PMEVTYPER1, Cluster Performance Monitors Event Type Registers

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CLUSTERPMU_PMEVTYPER2, Cluster Performance Monitors Event Type Registers

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CLUSTERPMU_PMEVTYPER3, Cluster Performance Monitors Event Type Registers

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CLUSTERPMU_PMEVTYPER4, Cluster Performance Monitors Event Type Registers

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CLUSTERPMU_PMEVTYPER5, Cluster Performance Monitors Event Type Registers

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CLUSTERPMU_PMEVCNTSR0, Cluster Performance Monitors Event Count Snapshot Registers

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CLUSTERPMU_PMEVCNTSR1, Cluster Performance Monitors Event Count Snapshot Registers

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CLUSTERPMU_PMEVCNTSR2, Cluster Performance Monitors Event Count Snapshot Registers

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CLUSTERPMU_PMEVCNTSR3, Cluster Performance Monitors Event Count Snapshot Registers

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CLUSTERPMU_PMEVCNTSR4, Cluster Performance Monitors Event Count Snapshot Registers

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CLUSTERPMU_PMEVCNTSR5, Cluster Performance Monitors Event Count Snapshot Registers

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CLUSTERPMU_PMSSSR, Cluster Performance Monitors Snapshot Status register

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CLUSTERPMU_PMOVSSR, Cluster Performance Monitors Overflow Status Snapshot register

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CLUSTERPMU_PMCNTENSET, Cluster Performance Monitors Count Enable Set register

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CLUSTERPMU_PMCNTENCLR, Cluster Performance Monitors Count Enable Clear register

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CLUSTERPMU_PMINTENSET, Cluster Performance Monitors Interrupt Enable Set register

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CLUSTERPMU_PMINTENCLR, Cluster Performance Monitors Interrupt Enable Clear register

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CLUSTERPMU_PMOVSCLR, Cluster Performance Monitors Overflow Flag Status Clear register

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CLUSTERPMU_PMOVSSET, Cluster Performance Monitors Overflow Flag Status Set register

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CLUSTERPMU_PMCEID0, Cluster Performance Monitors Common Event Identification register 0

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CLUSTERPMU_PMCEID1, Cluster Performance Monitors Common Event Identification register 1

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CLUSTERPMU_PMCEID2, Cluster Performance Monitors Common Event Identification register 2

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CLUSTERPMU_PMCEID3, Cluster Performance Monitors Common Event Identification register 3

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CLUSTERPMU_PMSSRR, Cluster Performance Monitors Snapshot Reset register

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CLUSTERPMU_PMDEVAFF0, Cluster Performance Monitors Device Affinity register 0

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CLUSTERPMU_PMDEVAFF1, Cluster Performance Monitors Device Affinity register 1

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CLUSTERPMU_PMDEVID, Cluster Performance Monitors Device ID register

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CLUSTERPMU_PMDEVTYPE, Cluster Performance Monitors Device Type register

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CLUSTERPMU_PMCIDR0, Cluster Performance Monitors Component Identification Register 0

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CLUSTERPMU_PMCIDR1, Cluster Performance Monitors Component Identification Register 1

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CLUSTERPMU_PMCIDR2, Cluster Performance Monitors Component Identification Register 2

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CLUSTERPMU_PMCIDR3, Cluster Performance Monitors Component Identification Register 3

# metadata.contentDescription
This manual is for system designers, system integrators, and programmers who are designing or programming a System on Chip (SoC) that uses a C1-DynamIQ™ Shared Unit along with an Arm core or cores, and one or two SME2 units.