# title
Arm CoreLink MHU-320AE Message Handling Unit Technical Reference Manual

# topic.label
Arm® CoreLink™ MHU-320AE Message Handling Unit Technical Reference Manual

# topic.topics[].topics[].topics[].topics[].label
Doorbell channel error recovery procedure

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Error recovery and fault handling interrupts

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MHU Sender and MHU Receiver software error records, Record 0

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Uncorrectable MHU Receiver error record 1 in MHU Sender

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MHU Sender FIFO channel RAM error records 2 and 3

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Uncorrectable MHU Sender error record 1 in MHU Receiver

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MHU Receiver doorbell channel RAM error records 2 and 3

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MHU Receiver fast channel RAM error records 4 and 5

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MHU Receiver FIFO channel configuration RAM error records 6 and 7

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MHU Receiver FIFO channel data RAM error records 8 and 9

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FMU_ERR<n>FR, Error Record <n> Feature Register, n = 0 - 5

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FMU_ERR<n>CTLR, Error Record <n> Control Register, n = 0 - 5

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FMU_ERR<n>STATUS, Error Record <n> Status Register, n = 0 - 5

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FMU_SMEN, Safety Mechanism Enable Register

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FMU_SMERR, Safety Mechanism Error Register

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FMU_SMCR, Safety Mechanism Set Criticality Register

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FMU_SMWR, Safety Mechanism Page Write Register

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FMU_SMWDATA, Safety Mechanism Page Write Data Register

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FMU_SMRD, Safety Mechanism Page Read Register

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FMU_SMRDATA, Safety Mechanism Page Read Data Register

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FMU_TIMEOUT, FMU Timeout Duration Register

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FMU_ERRUPDATE, FMU Error Update Register

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FMU_PIDR4, MHU FMU Peripheral ID 4 Register

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FMU_PIDR5, MHU FMU Peripheral ID 5 Register

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FMU_PIDR6, MHU FMU Peripheral ID 6 Register

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FMU_PIDR7, MHU FMU Peripheral ID 7 Register

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FMU_PIDR0, MHU FMU Peripheral ID 0 Register

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FMU_PIDR1, MHU FMU Peripheral ID 1 Register

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FMU_PIDR2, MHU FMU Peripheral ID 2 Register

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FMU_PIDR3, MHU FMU Peripheral ID 3 Register

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FMU_CIDR0, MHU FMU Component ID 0 Register

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FMU_CIDR1, MHU FMU Component ID 1 Register

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FMU_CIDR2, MHU FMU Component ID 2 Register

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FMU_CIDR3, MHU FMU Component ID 3 Register

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MHU Sender Security Control register summary

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SSC_BLK_ID, Sender Security Control Block Identifier Register

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SSC_FEAT_SPT0, Sender Security Feature Support 0 Register

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SSC_FEAT_SPT1, Sender Security Feature Support 1 Register

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SSC_DBCH_CFG0, Sender Security Control Doorbell Channel Configuration 0 Register

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SSC_FFCH_CFG0, Sender Security Control FIFO Channel Configuration 0 Register

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SSC_FCH_CFG0, Sender Security Control Fast Channel Configuration 0 Register

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SSC_PBX_SG<n>, Sender Postbox Security Group n Register, n = 0

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SSC_PIDR4, Sender Security Peripheral ID 4 Register

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SSC_PIDR5, Sender Security Peripheral ID 5 Register

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SSC_PIDR6, Sender Security Peripheral ID 6 Register

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SSC_PIDR7, Sender Security Peripheral ID 7 Register

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SSC_PIDR0, Sender Security Peripheral ID 0 Register

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SSC_PIDR1, Sender Security Peripheral ID 1 Register

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SSC_PIDR2, Sender Security Peripheral ID 2 Register

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SSC_PIDR3, Sender Security Peripheral ID 3 Register

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SSC_CIDR0, Sender Security Component ID 0 Register

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SSC_CIDR1, Sender Security Component ID 1 Register

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SSC_CIDR2, Sender Security Component ID 2 Register

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SSC_CIDR3, Sender Security Component ID 3 Register

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PBX_BLK_ID, Postbox Block Identifier Register

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PBX_FEAT_SPT0, Postbox Feature Support 0 Register

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PBX_FEAT_SPT1, Postbox Feature Support 1 Register

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PBX_DBCH_CFG0, Postbox Doorbell Channel Configuration 0 Register

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PBX_FFCH_CFG0, Postbox FIFO Channel Configuration 0 Register

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PBX_FCH_CFG0, Postbox Fast Channel Configuration 0 Register

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PBX_DBCH_INT_ST<n>, Postbox Doorbell Channel Interrupt Status n Register, n = 0 - 3

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PBX_FFCH_INT_ST<n>, Postbox FIFO Channel Interrupt Status n Register, n = 0 - 1

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PBX_PIDR4, Postbox Peripheral ID 4 Register

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PBX_PIDR5, Postbox Peripheral ID 5 Register

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PBX_PIDR6, Postbox Peripheral ID 6 Register

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PBX_PIDR7, Postbox Peripheral ID 7 Register

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PBX_PIDR0, Postbox Peripheral ID 0 Register

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PBX_PIDR1, Postbox Peripheral ID 1 Register

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PBX_PIDR2, Postbox Peripheral ID 2 Register

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PBX_PIDR3, Postbox Peripheral ID 3 Register

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PBX_CIDR0, Postbox Component ID 0 Register

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PBX_CIDR1, Postbox Component ID 1 Register

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PBX_CIDR2, Postbox Component ID 2 Register

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PBX_CIDR3, Postbox Component ID 3 Register

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PDBCW<n>_ST, Postbox Doorbell Channel Window <n> Status Register, n = 0 - 127

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PDBCW<n>_SET, Postbox Doorbell Channel Window <n> Set Register, n = 0 - 127

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PDBCW<n>_INT_ST, Postbox Doorbell Channel Window <n> Interrupt Status Register, n = 0 - 127

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PDBCW<n>_INT_CLR, Postbox Doorbell Channel Window <n> Interrupt Clear Register, n = 0 - 127

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PDBCW<n>_INT_EN, Postbox Doorbell Channel Window <n> Interrupt Enable Register, n = 0 - 127

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PDBCW<n>_CTRL, Postbox Doorbell Channel Window <n> Control Register, n = 0 - 127

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PFFCW<n>_PAY64, Postbox FIFO Channel Window <n> Payload Register (64bit access), n = 0 - 63

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PFFCW<n>_PAY32, Postbox FIFO Channel Window <n> Payload Register (32bit access), n = 0 - 63

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PFFCW<n>_FLG, Postbox FIFO Channel Window <n> Flag Register, n = 0 - 63

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PFFCW<n>_INT_ST, Postbox FIFO Channel Window <n> Interrupt Status Register, n = 0 - 63

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PFFCW<n>_INT_CLR, Postbox FIFO Channel Window <n> Interrupt Clear Register, n = 0 - 63

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PFFCW<n>_INT_EN, Postbox FIFO Channel Window <n> Interrupt Enable Register, n = 0 - 63

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PFFCW<n>_CTRL, Postbox FIFO Channel Window <n> Control Register, n = 0 - 63

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PFFCW<n>_ST, Postbox FIFO Channel Window <n> Status Register, n = 0 - 63

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PFFCW<n>_ACK_CNT, Postbox FIFO Channel Window <n> Acknowledge Counter Register, n = 0 - 63

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PFFCW<n>_TIDE, Postbox FIFO Channel Window <n> Tidemark Register, n = 0 - 63

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PFCW<n>_PAY32, Postbox Fast Channel Window <n> Payload 32bit Register, n = 0 - 1023

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PFCW<n>_PAY64, Postbox Fast Channel Window <n> Payload 64bit Register, n = 0 - 511

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PBX_FCTRL, Postbox Feature Control Register

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PBX_FIFO_ERRINS, Postbox FIFO channel RAM ECC Error Insertion Register

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SRAS_ERR<n>FR, Error Record <n> Feature Register, n = 0 - 3

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SRAS_ERR<n>CTLR, Error Record <n> Control Register, n = 0 - 3

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SRAS_ERR<n>STATUS, Error Record <n> Status Register, n = 0 - 3

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SRAS_ERR<n>ADDR, Error Record <n> Address Register, n = 0 - 3

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SRAS_ERR<n>MISC0, Error Record <n> Miscellaneous Register 0, n = 0 - 3

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SRAS_ERR<n>MISC1, Error Record <n> Miscellaneous Register 1, n = 0 - 3

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SRAS_ERR<n>MISC2, Error Record <n> Miscellaneous Register 2, n = 0 - 3

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SRAS_ERR<n>MISC3, Error Record <n> Miscellaneous Register 3, n = 0 - 3

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SRAS_ERRGSR, Error Group Status Register

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SRAS_ERRPIDR4, Sender RAS Peripheral ID 4 Register

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SRAS_ERRPIDR5, Sender RAS Peripheral ID 5 Register

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SRAS_ERRPIDR6, Sender RAS Peripheral ID 6 Register

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SRAS_ERRPIDR7, Sender RAS Peripheral ID 7 Register

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SRAS_ERRPIDR0, Sender RAS Peripheral ID 0 Register

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SRAS_ERRPIDR1, Sender RAS Peripheral ID 1 Register

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SRAS_ERRPIDR2, Sender RAS Peripheral ID 2 Register

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SRAS_ERRPIDR3, Sender RAS Peripheral ID 3 Register

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SRAS_ERRCIDR0, Sender RAS Component ID 0 Register

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SRAS_ERRCIDR1, Sender RAS Component ID 1 Register

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SRAS_ERRCIDR2, Sender RAS Component ID 2 Register

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SRAS_ERRCIDR3, Sender RAS Component ID 3 Register

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MHU Receiver Security Control register summary

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RSC_BLK_ID, Receiver Security Control Block Identifier Register

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RSC_FEAT_SPT0, Receiver Security Feature Support 0 Register

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RSC_FEAT_SPT1, Receiver Security Feature Support 1 Register

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RSC_DBCH_CFG0, Receiver Security Control Doorbell Channel Configuration 0 Register

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RSC_FFCH_CFG0, Receiver Security Control FIFO Channel Configuration 0 Register

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RSC_FCH_CFG0, Receiver Security Control Fast Channel Configuration 0 Register

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RSC_MBX_SG<n>, Receiver Mailbox Security Group <n> Register, n = 0

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RSC_PIDR4, Receiver Security Peripheral ID 4 Register

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RSC_PIDR5, Receiver Security Peripheral ID 5 Register

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RSC_PIDR6, Receiver Security Peripheral ID 6 Register

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RSC_PIDR7, Receiver Security Peripheral ID 7 Register

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RSC_PIDR0, Receiver Security Peripheral ID 0 Register

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RSC_PIDR1, Receiver Security Peripheral ID 1 Register

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RSC_PIDR2, Receiver Security Peripheral ID 2 Register

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RSC_PIDR3, Receiver Security Peripheral ID 3 Register

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RSC_CIDR0, Receiver Security Component ID 0 Register

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RSC_CIDR1, Receiver Security Component ID 1 Register

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RSC_CIDR2, Receiver Security Component ID 2 Register

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RSC_CIDR3, Receiver Security Component ID 3 Register

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MBX_BLK_ID, Mailbox Block Identifier Register

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MBX_FEAT_SPT0, Mailbox Feature Support 0 Register

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MBX_FEAT_SPT1, Mailbox Feature Support 1 Register

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MBX_DBCH_CFG0, Mailbox Doorbell Channel Configuration 0 Register

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MBX_FFCH_CFG0, Mailbox FIFO Channel Configuration 0 Register

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MBX_FCH_CFG0, Mailbox Fast Channel Configuration 0 Register

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MBX_FCH_CTRL, Mailbox Fast Channel Control Register

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MBX_FCG_INT_EN, Mailbox Fast Channel Group Interrupt Enable Register

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MBX_DBCH_INT_ST<n>, Mailbox Doorbell Channel Interrupt Status <n> Register, n = 0 - 3

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MBX_FFCH_INT_ST<n>, Mailbox FIFO Channel Interrupt Status <n> Register, n = 0 - 1

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MBX_FCG_INT_ST, Mailbox Fast Channel Group Interrupt Status Register

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MBX_FCH_GRP<n>_INT_ST, Mailbox Fast Channel Group <n> Interrupt Status Register, n = 0 - 31

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MBX_PIDR4, Mailbox Peripheral ID 4 Register

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MBX_PIDR5, Mailbox Peripheral ID 5 Register

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MBX_PIDR6, Mailbox Peripheral ID 6 Register

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MBX_PIDR7, Mailbox Peripheral ID 7 Register

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MBX_PIDR0, Mailbox Peripheral ID 0 Register

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MBX_PIDR1, Mailbox Peripheral ID 1 Register

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MBX_PIDR2, Mailbox Peripheral ID 2 Register

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MBX_PIDR3, Mailbox Peripheral ID 3 Register

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MBX_CIDR0, Mailbox Component ID 0 Register

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MBX_CIDR1, Mailbox Component ID 1 Register

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MBX_CIDR2, Mailbox Component ID 2 Register

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MBX_CIDR3, Mailbox Component ID 3 Register

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MDBCW<n>_ST, Mailbox Doorbell Channel Window <n> Status Register, n = 0 - 127

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MDBCW<n>_ST_MSK, Mailbox Doorbell Channel Window <n> Status Masked Register, n = 0 - 127

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MDBCW<n>_CLR, Mailbox Doorbell Channel Window <n> Clear Register, n = 0 - 127

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MDBCW<n>_MSK_ST, Mailbox Doorbell Channel Window <n> Mask Status Register, n = 0 - 127

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MDBCW<n>_MSK_SET, Mailbox Doorbell Channel Window <n> Mask Set Register, n = 0 - 127

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MDBCW<n>_MSK_CLR, Mailbox Doorbell Channel Window <n> Mask Clear Register, n = 0 - 127

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MDBCW<n>_CTRL, Mailbox Doorbell Channel Window <n> Control Register, n = 0 - 127

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MFFCW<n>_PAY64, Mailbox FIFO Channel Window <n> Payload Register (64bit access), n = 0 - 63

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MFFCW<n>_PAY32, Mailbox FIFO Channel Window <n> Payload Register (32bit access), n = 0 - 63

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MFFCW<n>_FLG64, Mailbox FIFO Channel Window <n> Flag Register (64bit access), n = 0 - 63

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MFFCW<n>_FLG32, MailboxPostbox FIFO Channel Window <n> Flag Register (32bit access), n = 0 - 63

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MFFCW<n>_INT_ST, Mailbox FIFO Channel Window <n> Interrupt Status Register, n = 0 - 63

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MFFCW<n>_INT_CLR, Mailbox FIFO Channel Window <n> Interrupt Clear Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].label
MFFCW<n>_INT_EN, Mailbox FIFO Channel Window <n> Interrupt Enable Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].label
MFFCW<n>_CTRL, Mailbox FIFO Channel Window <n> Control Register, n = 0 - 63

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MFFCW<n>_ST, Mailbox FIFO Channel Window <n> Status Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].label
MFFCW<n>_FIFO_POP, Mailbox FIFO Channel Window <n> FIFO POP Register, n = 0 - 63

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MFFCW<n>_TIDE, Mailbox FIFO Channel Window <n> Tidemark Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].label
MFCW<n>_PAY32, Mailbox Fast Channel Window <n> Payload 32bit Register, n = 0 - 1023

# topic.topics[].topics[].topics[].topics[].label
MFCW<n>_PAY64, Mailbox Fast Channel Window <n> Payload 64bit Register, n = 0 - 511

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MBX_FCTRL, Mailbox Feature Control Register

# topic.topics[].topics[].topics[].topics[].label
MBX_DB_ERRINS, Mailbox doorbell channel RAM ECC Error Insertion Register

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MBX_FST_ERRINS, Mailbox fast channel RAM ECC Error Insertion Register

# topic.topics[].topics[].topics[].topics[].label
MBX_FCFG_ERRINS, Mailbox FIFO channel config RAM ECC Error Insertion Register

# topic.topics[].topics[].topics[].topics[].label
MBX_FDATA_ERRINS, Mailbox FIFO channel data RAM ECC Error Insertion Register

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RRAS_ERR<n>FR, Error Record <n> Feature Register, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].label
RRAS_ERR<n>CTLR, Error Record <n> Control Register, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].label
RRAS_ERR<n>STATUS, Error Record <n> Status Register, n = 0 - 9

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RRAS_ERR<n>ADDR, Error Record <n> Address Register, n = 0 - 9

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RRAS_ERR<n>MISC0, Error Record <n> Miscellaneous Register 0, n = 0 - 9

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RRAS_ERR<n>MISC1, Error Record <n> Miscellaneous Register 1, n = 0 - 9

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RRAS_ERR<n>MISC2, Error Record <n> Miscellaneous Register 2, n = 0 - 9

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RRAS_ERR<n>MISC3, Error Record <n> Miscellaneous Register 3, n = 0 - 9

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RRAS_ERRGSR, Error Group Status Register

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RRAS_ERRPIDR4, Receiver RAS Peripheral ID 4 Register

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RRAS_ERRPIDR5, Receiver RAS Peripheral ID 5 Register

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RRAS_ERRPIDR6, Receiver RAS Peripheral ID 6 Register

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RRAS_ERRPIDR7, Receiver RAS Peripheral ID 7 Register

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RRAS_ERRPIDR0, Receiver RAS Peripheral ID 0 Register

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RRAS_ERRPIDR1, Receiver RAS Peripheral ID 1 Register

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RRAS_ERRPIDR2, Receiver RAS Peripheral ID 2 Register

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RRAS_ERRPIDR3, Receiver RAS Peripheral ID 3 Register

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RRAS_ERRCIDR0, Receiver RAS Component ID 0 Register

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RRAS_ERRCIDR1, Receiver RAS Component ID 1 Register

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RRAS_ERRCIDR2, Receiver RAS Component ID 2 Register

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RRAS_ERRCIDR3, Receiver RAS Component ID 3 Register

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Error signaling from a MHU-320AE block to the FMU

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Enable or disable a protection mechanism

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Enable or disable both error signals on a block

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Inject an error in a protection mechanism

# metadata.contentDescription
MHU-320AE Message Handling Unit provides services for message transfer through multiple channels and channel types, interrupt generation, registers, and programming.