# title
Arm Corstone Reference Systems Architecture Specification Ma2

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Arm® Corstone™ Reference Systems Architecture Specification Ma2

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Trusted Base System Architecture for Armv8-M

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Processor Custom Datapath Extension interface

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Security Alarm Manager incoming events allocation

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Security Alarm Manager Response Action settings

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Controlling the PD_VMR<i> power mode when striping

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Controlling the PD_CPU<n>RAM power states

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Controlling the PD_CPU<n>EPU power states

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Controlling the PD_VMR<i> power mode when striping

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P-Channel and Q-Channel Device interfaces

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Clock control Q-Channel device interfaces

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Power Control Q-Channel and P-Channel Expansion Device interfaces

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Power Control P-Channel Expansion Device interfaces

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Power Control Wakeup Q-Channel Device interfaces

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Clock Control Q-Channel Control interfaces

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Expansion Power Control Dependency interface

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CPU<n> External Peripheral interface EPPB

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Lifecycle Manager Lifecycle Indication interface

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Lifecycle Manager Debug Control Unit interface

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Lifecycle Manager Non-Volatile Memory interface

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Main Interconnect Peripheral Protection Controller Expansion

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Key Management Unit related configurations

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Security Alarm Manager related configurations

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Secure Access Configuration Register block

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Non-secure Access Configuration Register block

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CoreSight SoC-600M based Debug System not implemented

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CoreSight SoC-600M based Debug System implemented

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CPU<n>ROM, CPU<n> Debug System ROM

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CNTSCR0, CNTSCR1, Counter Scaling registers

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CNTPCT, Counter-timer Physical Count register

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CNTP_TVAL, Counter-timer Physical Timer TimerValue register

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CNTP_CTL, Counter-timer Physical Timer Control register

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WCS, Watchdog Control and Status register

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Technical changes between CRSAS Ma1 and Ma2

# metadata.contentDescription
This architecture specification is used to build reference subsystems that form the core of a full system.