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SystemReady Pre-Silicon BSA and SBSA Integration and Testing Guide

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SystemReady Pre-Silicon BSA and SBSA Integration and Testing Guide

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SystemReady pre-silicon compliance testing and the silicon journey

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Presenting an on-chip peripheral as a PCIe device

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Issue 1 - Non-contiguous configuration space as the ECAM region for endpoints or switches under the Root Port hierarchy

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Issue 2 - Non-compliance with completion handling of configuration reads

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Issue 3 - PCIe Root Port configuration space supports only 32-bit R/W access

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Issue 4 - Root Port exposes ATS and PRI capabilities

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Issue 5 - Enumeration code reports valid entries for device 1 to device 31 on bus 0

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Issue 6 - ATC invalidate all command sent by SMMU does not automatically translate the address field

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Issue 7 - Alternate Routing ID (ARI) mode handling

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Issue 8 - Incorrect type (Type 0 or Type 1) conversion for downstream configuration requests

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Issue 9 - Support for message-based interrupts

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Issue 10 - Completion timeout response type

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Issue 11 - PCIe response of Cpl-SC and not CplD-SC for bad ATS Translation Requests

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Issue 12 - PCIe Root Port supports only 32-bit aligned R/W access

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Why is pre-silicon BSA compliance testing needed?

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Overview of the pre-silicon BSA compliance solution

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Compliance test software stack for exerciser with a UEFI shell application

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How to access pre-silicon BSA compliance tests

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Running BSA ACS tests on the Arm Neoverse V3 reference design (RD-V3) Fixed Virtual Platform (FVP) model

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Arm SystemReady Pre-Silicon Compliance Checklist

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This guide outlines the IP and system integration steps needed to develop an SoC that is BSA compliant and suitable for SystemReady compliance.