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Arm CoreLink NI-710AE Network-on-Chip Interconnect Technical Reference Manual

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Arm® CoreLink™ NI-710AE Network-on-Chip Interconnect Technical Reference Manual

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Memory access protection and the Access Protection Unit

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Defining address ranges for APU address regions

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Specifying entities and access permissions for APU address regions

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Order of programming for APU address region registers

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Support for the APU 4K page as a child node of the endpoint node register

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Device isolation with IDM wire interface

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Controlling which safety mechanisms report errors to the FMU

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Power state requirements and characteristics

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Node, interface, and transaction identifiers

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Upsizing AXI and ACE-Lite data width function

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Downsizing AXI and ACE-Lite data width function

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Conditions for using read data aggregation

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Support for transporting data parity, ECC, and poison information

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Security access permissions of AXI requests

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Security access permissions of AHB requests

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Security access permissions of APB requests

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Register security attribute and security classification

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Interrupt and error logging register security

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Hardware-initiated entry based on timeout detection

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Soft reset use case examples for xSNIs and xMNIs

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Access control use case example for xMNIs and xSNIs

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Calculating TSPEC parameters for traffic

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QoS value override programmable registers

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Memory System Resource Partitioning and Monitoring

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Read and write bandwidth at ASNI and AMNI

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Delays at ASNI and AMNI because of backpressure

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Delays at ASNI because of structural backpressure

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Read and write bandwidth at HSNI and HNMI

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Delays at HSNI and HMNI because of backpressure

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Delays at HSNI because of structural backpressure

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IDM error logging interrupts and status flags

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Requirements of configuration register reads and writes

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Voltage domain configuration register region

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Power domain configuration register region

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Clock domain configuration register region

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Configuration address space example for design with multiple voltage, power, and clock domains

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Signal timing constraints and clock associations

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ASNI external interface types and associated signal groups

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ASNI AXI5 extension write address channel signals

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ASNI ACE-Lite write address channel signals

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ASNI ACE5-Lite extension write address channel signals

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ASNI AXI5 extension write data channel signals

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ASNI AXI4 write response channel signals

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ASNI AXI5 extension write response channel signals

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ASNI ACE5-Lite extension write response channel signals

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ASNI AXI5 extension read address channel signals

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ASNI ACE-Lite read address channel signals

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ASNI AXI5 extension read data channel signals

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ASNI Cortex-R52 and Cortex-R52+ AXIM interface signals

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ASNI AXIM write response channel signals

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ASNI LLPP write response channel signals

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AMNI external interface types and associated signal groups

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AMNI AXI5 extension write address channel signals

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AMNI ACE-Lite write address channel signals

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AMNI ACE5-Lite extension write address channel signals

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AMNI AXI5 extension write data channel signals

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AMNI AXI4 write response channel signals

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AMNI AXI5 extension write response channel signals

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AMNI AXI5 extension read address channel signals

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AMNI ACE-Lite read address channel signals

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AMNI AXI5 extension read data channel signals

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AMNI AXI3 interface configuration signal changes

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AMNI AXIS write response channel signals

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HSNI external interface types and associated signal groups

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HMNI external interface types and associated signal groups

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PMNI external interface types and associated signal groups

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Debug and Performance Monitoring Unit interface signals

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Access Protection Unit interface signals

# metadata.contentDescription
This manual is for the Arm CoreLink NI‑710AE Network‑on‑Chip Interconnect. The manual describes the features and functionality of the product, and contains programming information.