# title
Arm Cortex-R82 Processor Technical Reference Manual

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Arm® Cortex®-R82 Processor Technical Reference Manual

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 Rules governing cluster PPU mode transitions

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Cluster power mode and core power mode dependencies

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Encodings for cluster power modes and operating modes

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Programming sequences for the cluster and the core

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Programming sequence to bring the cluster and cores from Off to On mode

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Programming sequence to bring the cluster and cores from On to Off mode

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Programming sequence for an interrupt controller to bring cores and cluster to On or Off mode

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Explicit resetting of cluster and cores and debug recovery

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Implications of not having a System Control Processor

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PPU and reset management register summary

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Instruction cache speculative memory accesses

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Instructions implemented by the L1 memory system

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Temporal freedom from interference between a rich context and a partially real-time context

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Temporal freedom of interference between a fully real-time context and less deterministic contexts

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Ensuring temporal freedom of interference in a hypervisor

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Ensuring temporal freedom of interference while sharing data

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Memory behavior and supported memory types

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Error reporting and performance monitoring

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External access permissions to debug registers

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Supported debug and trace trigger events

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External register access permissions to the PMU registers

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Recommended implementation defined core PMU events

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Implementation defined cluster PMU events

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Recommended implementation defined cluster PMU events

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ETM trace unit generation options and resources

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Advanced SIMD and floating-point support

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About the Advanced SIMD and floating-point support

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AArch64 Generic System Control registers summary

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AArch64 Performance Monitors registers summary

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AArch64 Other system control registers summary

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ID_PFR0_EL1, AArch32 Processor Feature Register 0

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ID_PFR1_EL1, AArch32 Processor Feature Register 1

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ID_DFR0_EL1, AArch32 Debug Feature Register 0

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ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0

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ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0

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ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1

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ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2

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ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3

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ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0

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ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1

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ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2

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ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3

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ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4

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ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5

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ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4

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ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6

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MVFR0_EL1, AArch32 Media and VFP Feature Register 0

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MVFR1_EL1, AArch32 Media and VFP Feature Register 1

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MVFR2_EL1, AArch32 Media and VFP Feature Register 2

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ID_PFR2_EL1, AArch32 Processor Feature Register 2

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ID_MMFR5_EL1, AArch32 Memory Model Feature Register 5

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ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0

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ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1

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ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0

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ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1

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ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0

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ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1

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ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0

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ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1

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ID_AA64ISAR2_EL1, AArch64 Instruction Set Attribute Register 2

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ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0

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ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1

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ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2

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ID_AA64MMFR3_EL1, AArch64 Memory Model Feature Register 3

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CCSIDR_EL1, Current Cache Size ID Register

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CSSELR_EL1, Cache Size Selection Register

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VPIDR_EL2, Virtualization Processor ID Register

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AArch64 Generic System control register description

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SCTLR_EL1, System Control Register (EL1)

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ACTLR_EL1, Auxiliary Control Register (EL1)

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CPACR_EL1, Architectural Feature Access Control Register

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TTBR0_EL1, Translation Table Base Register 0 (EL1)

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TTBR1_EL1, Translation Table Base Register 1 (EL1)

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TCR_EL1, Translation Control Register (EL1)

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APIAKeyLo_EL1, Pointer Authentication Key A for Instruction (bits[63:0]) 

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APIAKeyHi_EL1, Pointer Authentication Key A for Instruction (bits[127:64]) 

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APIBKeyLo_EL1, Pointer Authentication Key B for Instruction (bits[63:0]) 

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APIBKeyHi_EL1, Pointer Authentication Key B for Instruction (bits[127:64]) 

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APDAKeyLo_EL1, Pointer Authentication Key A for Data (bits[63:0]) 

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APDAKeyHi_EL1, Pointer Authentication Key A for Data (bits[127:64]) 

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APDBKeyLo_EL1, Pointer Authentication Key B for Data (bits[63:0]) 

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APDBKeyHi_EL1, Pointer Authentication Key B for Data (bits[127:64]) 

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APGAKeyLo_EL1, Pointer Authentication Key A for Code (bits[63:0]) 

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APGAKeyHi_EL1, Pointer Authentication Key A for Code (bits[127:64]) 

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AFSR0_EL1, Auxiliary Fault Status Register 0 (EL1)

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AFSR1_EL1, Auxiliary Fault Status Register 1 (EL1)

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ESR_EL1, Exception Syndrome Register (EL1)

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PRBAR<n>_EL1, Protection Region Base Address Register n (EL1), n = 1 - 15

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PRLAR<n>_EL1, Protection Region Limit Address Register n (EL1), n = 1 - 15

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PRENR_EL1, Protection Region Enable Register (EL1)

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PRSELR_EL1, Protection Region Selection Register (EL1)

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PRBAR_EL1, Protection Region Base Address Register (EL1)

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PRLAR_EL1, Protection Region Limit Address Register (EL1)

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MAIR_EL1, Memory Attribute Indirection Register (EL1)

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AMAIR_EL1, Auxiliary Memory Attribute Indirection Register (EL1)

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VBAR_EL1, Vector Base Address Register (EL1)

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CONTEXTIDR_EL1, Context ID Register (EL1)

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TPIDR_EL1, EL1 Software Thread ID Register

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IMP_CPUACTLR_EL1, CPU Auxiliary Control Register

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IMP_CPUPWRCTLR_EL1, CPU Power Control Register

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IMP_CLUSTERSID_EL1, Cluster Scheme ID Register

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IMP_CLUSTERACPSID_EL1, Cluster ACP Scheme ID Register

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IMP_CLUSTERQOSR_EL1, Cluster Quality of Service Register

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IMP_CDBGDR0_EL1, Cache Debug Data Register 0

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IMP_CDBGDR1_EL1, Cache Debug Data Register 1

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IMP_CLUSTERCDBGDR0_EL1, Cluster Cache Debug Data Register 0

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IMP_CPUPCR_EL1, Selected Instruction Patch Control Register

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IMP_CPUPCR<n>_EL1, Instruction Patch Control Registers, n = 0 - 5

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IMP_CPUPOR_EL1, Selected Instruction Patch Opcode Register

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IMP_CPUPOR<n>_EL1, Instruction Patch Opcode Registers, n = 0 - 5

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IMP_CPUPMR_EL1, Selected Instruction Patch Mask Register

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IMP_CPUPMR<n>_EL1, Instruction Patch Mask Registers, n = 0 - 5

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TPIDR_EL0, EL0 Read/Write Software Thread ID Register

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TPIDRRO_EL0, EL0 Read-Only Software Thread ID Register

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ACTLR_EL2, Auxiliary Control Register (EL2)

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CPTR_EL2, Architectural Feature Trap Register (EL2)

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HACR_EL2, Hypervisor Auxiliary Control Register

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VSCTLR_EL2, Virtualization System Control Register (EL2)

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TCR_EL2, Translation Control Register (EL2)

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AFSR0_EL2, Auxiliary Fault Status Register 0 (EL2)

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AFSR1_EL2, Auxiliary Fault Status Register 1 (EL2)

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ESR_EL2, Exception Syndrome Register (EL2)

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PRBAR<n>_EL2, Protection Region Base Address Register n (EL2), n = 1 - 15

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PRLAR<n>_EL2, Protection Region Limit Address Register n (EL2), n = 1 - 15

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HPFAR_EL2, Hypervisor IPA Fault Address Register

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PRENR_EL2, Protection Region Enable Register (EL2)

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PRSELR_EL2, Protection Region Selection Register (EL2)

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PRBAR_EL2, Protection Region Base Address Register (EL2)

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PRLAR_EL2, Protection Region Limit Address Register (EL2)

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MAIR_EL2, Memory Attribute Indirection Register (EL2)

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AMAIR_EL2, Auxiliary Memory Attribute Indirection Register (EL2)

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VBAR_EL2, Vector Base Address Register (EL2)

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RVBAR_EL2, Reset Vector Base Address Register (if EL3 not implemented)

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RMR_EL2, Reset Management Register (EL2)

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CONTEXTIDR_EL2, Context ID Register (EL2)

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TPIDR_EL2, EL2 Software Thread ID Register

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PMINTENSET_EL1, Performance Monitors Interrupt Enable Set Register

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PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear Register

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IMP_CLUSTERPMCNTENSET_EL1, Cluster Performance Monitors Count Enable Set register

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IMP_CLUSTERPMCNTENCLR_EL1, Cluster Performance Monitors Count Enable Clear register

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IMP_CLUSTERPMOVSSET_EL1, Cluster Performance Monitors Overflow Flag Status Set register

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IMP_CLUSTERPMOVSCLR_EL1, Cluster Performance Monitors Overflow Flag Status Clear Register

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IMP_CLUSTERPMSELR_EL1, Cluster Performance Monitors Event Counter Selection Register

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IMP_CLUSTERPMXEVTYPER_EL1, Cluster Performance Monitors Selected Event Type Register

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IMP_CLUSTERPMXEVCNTR_EL1, Cluster Performance Monitors Selected Event Count Register

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IMP_CLUSTERPMCEID0_EL1, Cluster Performance Monitors Common Event Identification register 0

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IMP_CLUSTERPMCEID1_EL1, Cluster Performance Monitors Common Event Identification register 1

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PMCR_EL0, Performance Monitors Control Register

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PMCNTENSET_EL0, Performance Monitors Count Enable Set Register

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PMCNTENCLR_EL0, Performance Monitors Count Enable Clear Register

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PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear Register

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PMSELR_EL0, Performance Monitors Event Counter Selection Register

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PMCEID0_EL0, Performance Monitors Common Event Identification Register 0

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PMCEID1_EL0, Performance Monitors Common Event Identification Register 1

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PMCCNTR_EL0, Performance Monitors Cycle Count Register

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PMXEVTYPER_EL0, Performance Monitors Selected Event Type Register

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PMXEVCNTR_EL0, Performance Monitors Selected Event Count Register

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PMUSERENR_EL0, Performance Monitors User Enable Register

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PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set Register

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PMEVCNTR<n>_EL0, Performance Monitors Event Count Registers, n = 0 - 5

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PMEVTYPER<n>_EL0, Performance Monitors Event Type Registers, n = 0 - 5

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PMCCFILTR_EL0, Performance Monitors Cycle Count Filter Register

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AArch64 System instruction register description

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IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable

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IC IALLU, Instruction Cache Invalidate All to PoU

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DC IVAC, Data or unified Cache line Invalidate by VA to PoC

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DC ISW, Data or unified Cache line Invalidate by Set/Way

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AT S1E1R, Address Translate Stage 1 EL1 Read

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AT S1E1W, Address Translate Stage 1 EL1 Write

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AT S1E0R, Address Translate Stage 1 EL0 Read

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AT S1E0W, Address Translate Stage 1 EL0 Write

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AT S1E1RP, Address Translate Stage 1 EL1 Read PAN

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AT S1E1WP, Address Translate Stage 1 EL1 Write PAN

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DC CSW, Data or unified Cache line Clean by Set/Way

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DC CISW, Data or unified Cache line Clean and Invalidate by Set/Way

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TLBI VMALLE1OS, TLB Invalidate by VMID, All at stage 1, EL1, Outer Shareable

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TLBI VAE1OS, TLB Invalidate by VA, EL1, Outer Shareable

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TLBI ASIDE1OS, TLB Invalidate by ASID, EL1, Outer Shareable

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TLBI VAAE1OS, TLB Invalidate by VA, All ASID, EL1, Outer Shareable

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TLBI VALE1OS, TLB Invalidate by VA, Last level, EL1, Outer Shareable

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TLBI VAALE1OS, TLB Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable

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TLBI RVAE1IS, TLB Range Invalidate by VA, EL1, Inner Shareable

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TLBI RVAAE1IS, TLB Range Invalidate by VA, All ASID, EL1, Inner Shareable

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TLBI RVALE1IS, TLB Range Invalidate by VA, Last level, EL1, Inner Shareable

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TLBI RVAALE1IS, TLB Range Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable

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TLBI VMALLE1IS, TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable

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TLBI VAE1IS, TLB Invalidate by VA, EL1, Inner Shareable

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TLBI ASIDE1IS, TLB Invalidate by ASID, EL1, Inner Shareable

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TLBI VAAE1IS, TLB Invalidate by VA, All ASID, EL1, Inner Shareable

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TLBI VALE1IS, TLB Invalidate by VA, Last level, EL1, Inner Shareable

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TLBI VAALE1IS, TLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable

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TLBI RVAE1OS, TLB Range Invalidate by VA, EL1, Outer Shareable

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TLBI RVAAE1OS, TLB Range Invalidate by VA, All ASID, EL1, Outer Shareable

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TLBI RVALE1OS, TLB Range Invalidate by VA, Last level, EL1, Outer Shareable

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TLBI RVAALE1OS, TLB Range Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable

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TLBI RVAE1, TLB Range Invalidate by VA, EL1

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TLBI RVAAE1, TLB Range Invalidate by VA, All ASID, EL1

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TLBI RVALE1, TLB Range Invalidate by VA, Last level, EL1

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TLBI RVAALE1, TLB Range Invalidate by VA, All ASID, Last level, EL1

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TLBI VMALLE1, TLB Invalidate by VMID, All at stage 1, EL1

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TLBI ASIDE1, TLB Invalidate by ASID, EL1

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TLBI VAAE1, TLB Invalidate by VA, All ASID, EL1

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TLBI VALE1, TLB Invalidate by VA, Last level, EL1

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TLBI VAALE1, TLB Invalidate by VA, All ASID, Last level, EL1

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SYS IMP_BPI, Branch Predictor Invalidation Operation

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SYS IMP_CDBGDCT, L1 Data Cache Tag Read Operation

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SYS IMP_CDBGICT, L1 Instruction Cache Tag Read Operation

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SYS IMP_CLUSTERCDBGL2T, L2 Cache Tag Read Operation

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SYS IMP_CLUSTERCDBGL2DT, L2 Cache Duplicate L1 Tag Read Operation

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SYS IMP_CLUSTERCDBGLCUDT, LCU Duplicate L1 Tag Read Operation

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SYS IMP_CDBGDCD, L1 Data Cache Data Read Operation

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SYS IMP_CDBGICD, L1 Instruction Cache Data Read Operation

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SYS IMP_CLUSTERCDBGL2D, L2 Cache Data Read Operation

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CFP RCTX, Control Flow Prediction Restriction by Context

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DVP RCTX, Data Value Prediction Restriction by Context

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CPP RCTX, Cache Prefetch Prediction Restriction by Context

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IC IVAU, Instruction Cache line Invalidate by VA to PoU

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DC CVAC, Data or unified Cache line Clean by VA to PoC

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DC CVAU, Data or unified Cache line Clean by VA to PoU

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DC CVAP, Data or unified Cache line Clean by VA to PoP

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DC CVADP, Data or unified Cache line Clean by VA to PoDP

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DC CIVAC, Data or unified Cache line Clean and Invalidate by VA to PoC

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AT S1E2R, Address Translate Stage 1 EL2 Read

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AT S1E2W, Address Translate Stage 1 EL2 Write

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AT S12E1R, Address Translate Stages 1 and 2 EL1 Read

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AT S12E1W, Address Translate Stages 1 and 2 EL1 Write

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AT S12E0R, Address Translate Stages 1 and 2 EL0 Read

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AT S12E0W, Address Translate Stages 1 and 2 EL0 Write

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TLBI IPAS2E1IS, TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable

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TLBI RIPAS2E1IS, TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable

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TLBI IPAS2LE1IS, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable

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TLBI RIPAS2LE1IS, TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable

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TLBI ALLE2OS, TLB Invalidate All, EL2, Outer Shareable

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TLBI VAE2OS, TLB Invalidate by VA, EL2, Outer Shareable

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TLBI ALLE1OS, TLB Invalidate All, EL1, Outer Shareable

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TLBI VALE2OS, TLB Invalidate by VA, Last level, EL2, Outer Shareable

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TLBI VMALLS12E1OS, TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Outer Shareable

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TLBI RVAE2IS, TLB Range Invalidate by VA, EL2, Inner Shareable

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TLBI RVALE2IS, TLB Range Invalidate by VA, Last level, EL2, Inner Shareable

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TLBI ALLE2IS, TLB Invalidate All, EL2, Inner Shareable

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TLBI VAE2IS, TLB Invalidate by VA, EL2, Inner Shareable

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TLBI ALLE1IS, TLB Invalidate All, EL1, Inner Shareable

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TLBI VALE2IS, TLB Invalidate by VA, Last level, EL2, Inner Shareable

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TLBI VMALLS12E1IS, TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable

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TLBI IPAS2E1OS, TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable

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TLBI IPAS2E1, TLB Invalidate by Intermediate Physical Address, Stage 2, EL1

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TLBI RIPAS2E1, TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1

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TLBI RIPAS2E1OS, TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable

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TLBI IPAS2LE1OS, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable

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TLBI IPAS2LE1, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1

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TLBI RIPAS2LE1, TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1

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TLBI RIPAS2LE1OS, TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable

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TLBI RVAE2OS, TLB Range Invalidate by VA, EL2, Outer Shareable

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TLBI RVALE2OS, TLB Range Invalidate by VA, Last level, EL2, Outer Shareable

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TLBI RVAE2, TLB Range Invalidate by VA, EL2

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TLBI RVALE2, TLB Range Invalidate by VA, Last level, EL2

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TLBI VALE2, TLB Invalidate by VA, Last level, EL2

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TLBI VMALLS12E1, TLB Invalidate by VMID, All at Stage 1 and 2, EL1

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OSDTRRX_EL1, OS Lock Data Transfer Register, Receive

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MDCCINT_EL1, Monitor DCC Interrupt Enable Register

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MDSCR_EL1, Monitor Debug System Control Register

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OSDTRTX_EL1, OS Lock Data Transfer Register, Transmit

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OSECCR_EL1, OS Lock Exception Catch Control Register

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DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 - 5

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DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 - 5

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DBGWVR<n>_EL1, Debug Watchpoint Value Registers, n = 0 - 3

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DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 - 3

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MDRAR_EL1, Monitor Debug ROM Address Register

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DBGPRCR_EL1, Debug Power Control Register

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DBGCLAIMSET_EL1, Debug CLAIM Tag Set Register

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DBGCLAIMCLR_EL1, Debug CLAIM Tag Clear Register

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DBGDTR_EL0, Debug Data Transfer Register, half-duplex

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DBGDTRRX_EL0, Debug Data Transfer Register, Receive

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DBGDTRTX_EL0, Debug Data Transfer Register, Transmit

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TRFCR_EL1, Trace Filter Control Register (EL1)

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MDCR_EL2, Monitor Debug Configuration Register (EL2)

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TRFCR_EL2, Trace Filter Control Register (EL2)

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ICC_PMR_EL1, Interrupt Controller Interrupt Priority Mask Register

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ICV_PMR_EL1, Interrupt Controller Virtual Interrupt Priority Mask Register

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ICC_IAR0_EL1, Interrupt Controller Interrupt Acknowledge Register 0

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ICV_IAR0_EL1, Interrupt Controller Virtual Interrupt Acknowledge Register 0

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ICC_EOIR0_EL1, Interrupt Controller End Of Interrupt Register 0

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ICV_EOIR0_EL1, Interrupt Controller Virtual End Of Interrupt Register 0

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ICC_AP0R<n>_EL1, Interrupt Controller Active Priorities Group 0 Registers, n = 0

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ICV_AP0R<n>_EL1, Interrupt Controller Virtual Active Priorities Group 0 Registers, n = 0

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ICC_HPPIR0_EL1, Interrupt Controller Highest Priority Pending Interrupt Register 0

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ICV_HPPIR0_EL1, Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0

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ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0

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ICC_AP1R<n>_EL1, Interrupt Controller Active Priorities Group 1 Registers, n = 0

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ICV_AP1R<n>_EL1, Interrupt Controller Virtual Active Priorities Group 1 Registers, n = 0

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ICV_DIR_EL1, Interrupt Controller Deactivate Virtual Interrupt Register

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ICC_RPR_EL1, Interrupt Controller Running Priority Register

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ICV_RPR_EL1, Interrupt Controller Virtual Running Priority Register

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ICC_SGI1R_EL1, Interrupt Controller Software Generated Interrupt Group 1 Register

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ICC_ASGI1R_EL1, Interrupt Controller Alias Software Generated Interrupt Group 1 Register

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ICC_SGI0R_EL1, Interrupt Controller Software Generated Interrupt Group 0 Register

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ICC_IAR1_EL1, Interrupt Controller Interrupt Acknowledge Register 1

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ICV_IAR1_EL1, Interrupt Controller Virtual Interrupt Acknowledge Register 1

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ICC_EOIR1_EL1, Interrupt Controller End Of Interrupt Register 1

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ICV_EOIR1_EL1, Interrupt Controller Virtual End Of Interrupt Register 1

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ICC_HPPIR1_EL1, Interrupt Controller Highest Priority Pending Interrupt Register 1

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ICV_HPPIR1_EL1, Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1

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ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1

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ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1

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ICC_CTLR_EL1, Interrupt Controller Control Register (EL1)

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ICV_CTLR_EL1, Interrupt Controller Virtual Control Register

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ICC_SRE_EL1, Interrupt Controller System Register Enable Register (EL1)

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ICC_IGRPEN0_EL1, Interrupt Controller Interrupt Group 0 Enable register

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ICV_IGRPEN0_EL1, Interrupt Controller Virtual Interrupt Group 0 Enable register

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ICC_IGRPEN1_EL1, Interrupt Controller Interrupt Group 1 Enable register

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ICV_IGRPEN1_EL1, Interrupt Controller Virtual Interrupt Group 1 Enable register

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ICH_LR<n>_EL2, Interrupt Controller List Registers, n = 0 - 15

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ICH_AP0R<n>_EL2, Interrupt Controller Hyp Active Priorities Group 0 Registers, n = 0

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ICH_AP1R<n>_EL2, Interrupt Controller Hyp Active Priorities Group 1 Registers, n = 0

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ICC_SRE_EL2, Interrupt Controller System Register Enable Register (EL2)

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ICH_HCR_EL2, Interrupt Controller Hyp Control Register

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ICH_VTR_EL2, Interrupt Controller VGIC Type Register

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ICH_MISR_EL2, Interrupt Controller Maintenance Interrupt State Register

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ICH_EISR_EL2, Interrupt Controller End of Interrupt Status Register

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ICH_ELRSR_EL2, Interrupt Controller Empty List Register Status Register

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ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register

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ERRSELR_EL1, Error Record Select Register

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ERXFR_EL1, Selected Error Record Feature Register

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ERXCTLR_EL1, Selected Error Record Control Register

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ERXSTATUS_EL1, Selected Error Record Primary Status Register

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ERXADDR_EL1, Selected Error Record Address Register

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ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0

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ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1

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ERXMISC2_EL1, Selected Error Record Miscellaneous Register 2

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ERXMISC3_EL1, Selected Error Record Miscellaneous Register 3

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DISR_EL1, Deferred Interrupt Status Register

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VSESR_EL2, Virtual SError Exception Syndrome Register

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VDISR_EL2, Virtual Deferred Interrupt Status Register

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TRCSEQEVR<n>, Sequencer State Transition Control Register <n> , n = 0 - 2

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TRCCNTRLDVR<n>, Counter Reload Value Register <n> , n = 0 - 1

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TRCCNTCTLR<n>, Counter Control Register <n> , n = 0 - 1

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TRCCNTVR<n>, Counter Value Register <n> , n = 0 - 1

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TRCVICTLR, ViewInst Main Control Register

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TRCSEQRSTEVR, Sequencer Reset Control Register

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TRCVDCTLR, ViewData Main Control Register

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TRCEXTINSELR, External Input Select Register

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TRCVDSACCTLR, ViewData Include/Exclude Single Address Comparator Control Register

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TRCVDARCCTLR, ViewData Include/Exclude Address Range Comparator Control Register

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TRCBBCTLR, Branch Broadcast Control Register

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TRCSSCCR<n>, Single-shot Comparator Control Register <n> , n = 0 - 1

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TRCSSCSR<n>, Single-shot Comparator Control Status Register <n> , n = 0 - 1

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TRCRSCTLR<n>, Resource Selection Control Register <n> , n = 2 - 15

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TRCDVCVR<n>, Data Value Comparator Value Register <n> , n = 0 - 1

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TRCDVCMR<n>, Data Value Comparator Mask Register <n> , n = 0 - 1

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TRCACVR<n>, Address Comparator Value Register <n> , n = 0 - 7

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TRCACATR<n>, Address Comparator Access Type Register <n> , n = 0 - 7

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TRCCIDCCTLR0, Context Identifier Comparator Control Register 0

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TRCVMIDCCTLR0, Virtual Context Identifier Comparator Control Register 0

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TRCCIDCVR<n>, Context Identifier Comparator Value Registers <n> , n = 0

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TRCVMIDCVR<n>, Virtual Context Identifier Comparator Value Register <n> , n = 0

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AArch64 Special purpose register description

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SPSR_EL1, Saved Program Status Register (EL1)

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DSPSR_EL0, Debug Saved Program Status Register

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SPSR_EL2, Saved Program Status Register (EL2)

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SPSR_irq, Saved Program Status Register (IRQ mode)

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SPSR_abt, Saved Program Status Register (Abort mode)

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SPSR_und, Saved Program Status Register (Undefined mode)

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SPSR_fiq, Saved Program Status Register (FIQ mode)

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AArch64 Generic Timer register description

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CNTVCT_EL0, Counter-timer Virtual Count Register

# topic.topics[].topics[].topics[].topics[].label
CNTP_CTL_EL0, Counter-timer Physical Timer Control Register

# topic.topics[].topics[].topics[].topics[].label
CNTV_CTL_EL0, Counter-timer Virtual Timer Control Register

# topic.topics[].topics[].topics[].topics[].label
CNTHPS_TVAL_EL2, Counter-timer Secure Physical Timer TimerValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
CNTHPS_CTL_EL2, Counter-timer Secure Physical Timer Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
CNTHPS_CVAL_EL2, Counter-timer Secure Physical Timer CompareValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
SCTLR_EL2, System Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
HSTR_EL2, Hypervisor System Trap Register

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Register summaries for registers accessed over the Utility bus

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Register descriptions for registers accessed over the Utility bus

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ERR<n>FR, Error Record <n> Feature Register, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERR<n>CTLR, Error Record <n> Control Register, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERR<n>STATUS, Error Record <n> Primary Status Register, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERR<n>MISC0, Error Record <n> Miscellaneous Register 0, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERR<n>MISC1, Error Record <n> Miscellaneous Register 1, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERR<n>MISC2, Error Record <n> Miscellaneous Register 2, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERR<n>MISC3, Error Record <n> Miscellaneous Register 3, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERR<n>PFGF, Error Record <n> Pseudo-fault Generation Feature Register, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERR<n>PFGCTL, Error Record <n> Pseudo-fault Generation Control Register, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERR<n>PFGCDN, Error Record <n> Pseudo-fault Generation Countdown Register, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
ERRPIDR4, Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].topics[].label
ERRPIDR0, Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
ERRPIDR1, Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
ERRPIDR2, Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
ERRPIDR3, Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
ERRCIDR0, Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
ERRCIDR1, Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
ERRCIDR2, Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
ERRCIDR3, Component Identification Register 3

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PPU_PMER, Power Mode Emulation Enable Register

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PPU_DISR, Device Interface Input Current Status Register

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PPU_MISR, Miscellaneous Input Current Status Register

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PPU_PTCR, Power Mode Transition Register

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PPU_AIMR, Additional Interrupt Mask Register

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PPU_AISR, Additional Interrupt Status Register

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PPU_IESR, Input Edge Sensitivity Register

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PPU_OPSR, Operating Mode Active Edge Sensitivity Register

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PPU_FUNRR, Functional Retention RAM Configuration Register

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PPU_FULRR, Full Retention RAM Configuration Register

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PPU_MEMRR, Memory Retention RAM Configuration Register

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PPU_EDTR0, Power Mode Entry Delay Register 0

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PPU_EDTR1, Power Mode Entry Delay Register 1

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PPU_DCDR0, Device Control Delay Configuration Register 0

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PPU_DCDR1, Device Control Delay Configuration Register 1

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PPU_PIDR4, PPU Peripheral Identification Register 4

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PPU_PIDR5, PPU Peripheral Identification Register 5

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PPU_PIDR6, PPU Peripheral Identification Register 6

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PPU_PIDR7, PPU Peripheral Identification Register 7

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PPU_PIDR0, PPU Peripheral Identification Register 0

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PPU_PIDR1, PPU Peripheral Identification Register 1

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PPU_PIDR2, PPU Peripheral Identification Register 2

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PPU_PIDR3, PPU Peripheral Identification Register 3

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PPU_CIDR0, PPU Component Identification Register 0

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PPU_CIDR1, PPU Component Identification Register 1

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PPU_CIDR2, PPU Component Identification Register 2

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PPU_CIDR3, PPU Component Identification Register 3

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CLUSTERPPU_PMER, Power Mode Emulation Enable Register

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CLUSTERPPU_DISR, Device Interface Input Current Status Register

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CLUSTERPPU_MISR, Miscellaneous Input Current Status Register

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CLUSTERPPU_PTCR, Power Mode Transition Register

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CLUSTERPPU_IESR, Input Edge Sensitivity Register

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CLUSTERPPU_OPSR, Operating Mode Active Edge Sensitivity Register

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CLUSTERPPU_FULRR, Full Retention RAM Configuration Register

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CLUSTERPPU_EDTR0, Power Mode Entry Delay Register 0

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CLUSTERPPU_EDTR1, Power Mode Entry Delay Register 1

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CLUSTERPPU_DCDR0, Device Control Delay Configuration Register 0

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CLUSTERPPU_DCDR1, Device Control Delay Configuration Register 1

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CLUSTERPPU_IDR0, PPU Identification Register 0

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CLUSTERPPU_IDR1, PPU Identification Register 1

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CLUSTERPPU_PIDR4, PPU Peripheral Identification Register 4

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CLUSTERPPU_PIDR5, PPU Peripheral Identification Register 5

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CLUSTERPPU_PIDR6, PPU Peripheral Identification Register 6

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CLUSTERPPU_PIDR7, PPU Peripheral Identification Register 7

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CLUSTERPPU_PIDR0, PPU Peripheral Identification Register 0

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CLUSTERPPU_PIDR1, PPU Peripheral Identification Register 1

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CLUSTERPPU_PIDR2, PPU Peripheral Identification Register 2

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CLUSTERPPU_PIDR3, PPU Peripheral Identification Register 3

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Registers accessed over the Debug APB bus

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Register summaries for registers accessed over the Debug APB bus

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Register descriptions for registers accessed over the Debug APB bus

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EDESR, External Debug Event Status Register

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EDECR, External Debug Execution Control Register

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EDWAR, External Debug Watchpoint Address Register

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DBGDTRRX_EL0, Debug Data Transfer Register, Receive

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EDITR, External Debug Instruction Transfer Register

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EDSCR, External Debug Status and Control Register

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DBGDTRTX_EL0, Debug Data Transfer Register, Transmit

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EDRCR, External Debug Reserve Control Register

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EDECCR, External Debug Exception Catch Control Register

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EDPRCR, External Debug Power/Reset Control Register

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EDPRSR, External Debug Processor Status Register

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DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 - 5

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DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 - 5

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DBGWVR<n>_EL1, Debug Watchpoint Value Registers, n = 0 - 3

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DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 - 3

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EDPFR, External Debug Processor Feature Register

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EDAA32PFR, External Debug Auxiliary Processor Feature Register

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EDITCTRL, External Debug Integration mode Control register

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DBGCLAIMSET_EL1, Debug CLAIM Tag Set Register

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DBGCLAIMCLR_EL1, Debug CLAIM Tag Clear Register

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EDDEVAFF0, External Debug Device Affinity register 0

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EDDEVAFF1, External Debug Device Affinity register 1

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EDLAR, External Debug Lock Access Register

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EDLSR, External Debug Lock Status Register

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EDDEVARCH, External Debug Device Architecture Register

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EDDEVID2, External Debug Device ID register 2

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EDDEVID1, External Debug Device ID Register 1

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EDDEVID, External Debug Device ID register 0

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EDDEVTYPE, External Debug Device Type register

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EDPIDR4, External Debug Peripheral Identification Register 4

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EDPIDR0, External Debug Peripheral Identification Register 0

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EDPIDR1, External Debug Peripheral Identification Register 1

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EDPIDR2, External Debug Peripheral Identification Register 2

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EDPIDR3, External Debug Peripheral Identification Register 3

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EDCIDR0, External Debug Component Identification Register 0

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EDCIDR1, External Debug Component Identification Register 1

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EDCIDR2, External Debug Component Identification Register 2

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EDCIDR3, External Debug Component Identification Register 3

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CLUSTERPMU_PMEVCNTR<n>_EL1, Cluster Performance Monitors Event Count Registers, n = 0 - 5

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CLUSTERPMU_PMEVTYPER<n>_EL1, Cluster Performance Monitors Event Type Registers, n = 0 - 5

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CLUSTERPMU_PMCCFILTR_EL1, Cluster Performance Monitors Cycle Counter Filter Register

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CLUSTERPMU_PMCNTENSET_EL1, Cluster Performance Monitors Count Enable Set register

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CLUSTERPMU_PMCNTENCLR_EL1, Cluster Performance Monitors Count Enable Clear register

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CLUSTERPMU_PMOVSCLR_EL1, Cluster Performance Monitors Overflow Flag Status Clear register

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CLUSTERPMU_PMOVSSET_EL1, Cluster Performance Monitors Overflow Flag Status Set register

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CLUSTERPMU_PMCEID0, Cluster Performance Monitors Common Event Identification register 0

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CLUSTERPMU_PMCEID1, Cluster Performance Monitors Common Event Identification register 1

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CLUSTERPMU_PMCEID2, Cluster Performance Monitors Common Event Identification register 2

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CLUSTERPMU_PMCEID3, Cluster Performance Monitors Common Event Identification register 3

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CLUSTERPMU_PMITCTRL, Cluster Performance Monitors Integration mode Control register

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CLUSTERPMU_PMDEVAFF0, Cluster Performance Monitors Device Affinity register 0

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CLUSTERPMU_PMDEVAFF1, Cluster Performance Monitors Device Affinity register 1

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CLUSTERPMU_PMLAR, Cluster Performance Monitors Lock Access Register

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CLUSTERPMU_PMLSR, Cluster Performance Monitors Lock Status Register

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CLUSTERPMU_PMDEVID, Cluster Performance Monitors Device ID register

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CLUSTERPMU_PMDEVTYPE, Cluster Performance Monitors Device Type register

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CLUSTERPMU_PMCIDR0, Cluster Performance Monitors Component Identification Register 0

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CLUSTERPMU_PMCIDR1, Cluster Performance Monitors Component Identification Register 1

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CLUSTERPMU_PMCIDR2, Cluster Performance Monitors Component Identification Register 2

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CLUSTERPMU_PMCIDR3, Cluster Performance Monitors Component Identification Register 3

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DBROM_ROMENTRY0, DebugBlock ROM table Entry 0

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DBROM_ROMENTRY1, DebugBlock ROM table Entry 1

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DBROM_ROMENTRY2, DebugBlock ROM table Entry 2

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DBROM_ROMENTRY3, DebugBlock ROM table Entry 3

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DBROM_ROMENTRY4, DebugBlock ROM table Entry 4

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DBROM_ROMENTRY5, DebugBlock ROM table Entry 5

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DBROM_ROMENTRY6, DebugBlock ROM table Entry 6

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DBROM_ROMENTRY7, DebugBlock ROM table Entry 7

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DBROM_ROMENTRY8, DebugBlock ROM table Entry 8

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DBROM_ROMENTRY9, DebugBlock ROM table Entry 9

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DBROM_DBGPCR0, DebugBlock ROM table Debug Power Control Register 0

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DBROM_DBGPSR0, DebugBlock ROM table Debug Power Status Register 0

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DBROM_PRIDR0, DebugBlock ROM table Power Request ID Register 0

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DBROM_ITCTRL, DebugBlock ROM table Integration Mode Control Register

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DBROM_CLAIMSET, DebugBlock ROM table Claim Tag Set Register

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DBROM_CLAIMCLR, DebugBlock ROM table Claim Tag Clear Register

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DBROM_DEVAFF0, DebugBlock ROM table Device Affinity Register 0

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DBROM_DEVAFF1, DebugBlock ROM table Device Affinity Register 1

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DBROM_LAR, DebugBlock ROM table Software Lock Access Register

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DBROM_LSR, DebugBlock ROM table Software Lock Status Register

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DBROM_AUTHSTATUS, DebugBlock ROM table Authentication Status Register

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DBROM_DEVARCH, DebugBlock ROM table Device Architecture Register

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DBROM_DEVID2, DebugBlock ROM table Device Configuration Register 2

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DBROM_DEVID1, DebugBlock ROM table Device Configuration Register 1

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DBROM_DEVID, DebugBlock ROM table Device Configuration Register

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DBROM_DEVTYPE, DebugBlock ROM table Device Type Register

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DBROM_PIDR4, DebugBlock ROM table Peripheral Identification Register 4

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DBROM_PIDR5, DebugBlock ROM table Peripheral Identification Register 5

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DBROM_PIDR6, DebugBlock ROM table Peripheral Identification Register 6

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DBROM_PIDR7, DebugBlock ROM table Peripheral Identification Register 7

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DBROM_PIDR0, DebugBlock ROM table Peripheral Identification Register 0

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DBROM_PIDR1, DebugBlock ROM table Peripheral Identification Register 1

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DBROM_PIDR2, DebugBlock ROM table Peripheral Identification Register 2

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DBROM_PIDR3, DebugBlock ROM table Peripheral Identification Register 3

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DBROM_CIDR0, DebugBlock ROM table Component Identification Register 0

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DBROM_CIDR1, DebugBlock ROM table Component Identification Register 1

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DBROM_CIDR2, DebugBlock ROM table Component Identification Register 2

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DBROM_CIDR3, DebugBlock ROM table Component Identification Register 3

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CLUSTERROM_ROMENTRY0, Cluster ROM table Entry 0

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CLUSTERROM_ROMENTRY1, Cluster ROM table Entry 1

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CLUSTERROM_ROMENTRY2, Cluster ROM table Entry 2

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CLUSTERROM_ROMENTRY3, Cluster ROM table Entry 3

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CLUSTERROM_ROMENTRY4, Cluster ROM table Entry 4

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CLUSTERROM_ROMENTRY5, Cluster ROM table Entry 5

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CLUSTERROM_ROMENTRY6, Cluster ROM table Entry 6

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CLUSTERROM_ROMENTRY7, Cluster ROM table Entry 7

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CLUSTERROM_ROMENTRY8, Cluster ROM table Entry 8

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CLUSTERROM_ROMENTRY9, Cluster ROM table Entry 9

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CLUSTERROM_DBGPCR0, Cluster ROM table Debug Power Control Register 0

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CLUSTERROM_DBGPCR1, Cluster ROM table Debug Power Control Register 1

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CLUSTERROM_DBGPCR2, Cluster ROM table Debug Power Control Register 2

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CLUSTERROM_DBGPCR3, Cluster ROM table Debug Power Control Register 3

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CLUSTERROM_DBGPCR4, Cluster ROM table Debug Power Control Register 4

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CLUSTERROM_DBGPCR5, Cluster ROM table Debug Power Control Register 5

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CLUSTERROM_DBGPCR6, Cluster ROM table Debug Power Control Register 6

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CLUSTERROM_DBGPCR7, Cluster ROM table Debug Power Control Register 7

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CLUSTERROM_DBGPSR0, Cluster ROM table Debug Power Status Register 0

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CLUSTERROM_DBGPSR1, Cluster ROM table Debug Power Status Register 1

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CLUSTERROM_DBGPSR2, Cluster ROM table Debug Power Status Register 2

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CLUSTERROM_DBGPSR3, Cluster ROM table Debug Power Status Register 3

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CLUSTERROM_DBGPSR4, Cluster ROM table Debug Power Status Register 4

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CLUSTERROM_DBGPSR5, Cluster ROM table Debug Power Status Register 5

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CLUSTERROM_DBGPSR6, Cluster ROM table Debug Power Status Register 6

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CLUSTERROM_DBGPSR7, Cluster ROM table Debug Power Status Register 7

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CLUSTERROM_PRIDR0, Cluster ROM table Power Request ID Register 0

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CLUSTERROM_ITCTRL, Cluster ROM table Integration Mode Control Register

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CLUSTERROM_CLAIMSET, Cluster ROM table Claim Tag Set Register

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CLUSTERROM_CLAIMCLR, Cluster ROM table Claim Tag Clear Register

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CLUSTERROM_DEVAFF0, Cluster ROM table Device Affinity Register 0

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CLUSTERROM_DEVAFF1, Cluster ROM table Device Affinity Register 1

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CLUSTERROM_LAR, Cluster ROM table Software Lock Access Register

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CLUSTERROM_LSR, Cluster ROM table Software Lock Status Register

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CLUSTERROM_AUTHSTATUS, Cluster ROM table Authentication Status Register

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CLUSTERROM_DEVARCH, Cluster ROM table Device Architecture Register

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CLUSTERROM_DEVID2, Cluster ROM table Device Configuration Register 2

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CLUSTERROM_DEVID1, Cluster ROM table Device Configuration Register 1

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CLUSTERROM_DEVID, Cluster ROM table Device Configuration Register

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CLUSTERROM_DEVTYPE, Cluster ROM table Device Type Register

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_PIDR4, Cluster ROM table Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_PIDR5, Cluster ROM table Peripheral Identification Register 5

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_PIDR6, Cluster ROM table Peripheral Identification Register 6

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_PIDR7, Cluster ROM table Peripheral Identification Register 7

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_PIDR0, Cluster ROM table Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_PIDR1, Cluster ROM table Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_PIDR2, Cluster ROM table Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_PIDR3, Cluster ROM table Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_CIDR0, Cluster ROM table Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_CIDR1, Cluster ROM table Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_CIDR2, Cluster ROM table Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
CLUSTERROM_CIDR3, Cluster ROM table Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_ROMENTRY0, Core ROM table Entry 0

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_ROMENTRY1, Core ROM table Entry 1

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_ROMENTRY2, Core ROM table Entry 2

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_ROMENTRY3, Core ROM table Entry 3

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_PRIDR0, Core ROM table Power Request ID Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_ITCTRL, Core ROM table Integration Mode Control Register

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_CLAIMSET, Core ROM table Claim Tag Set Register

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_CLAIMCLR, Core ROM table Claim Tag Clear Register

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_DEVAFF0, Core ROM table Device Affinity Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_DEVAFF1, Core ROM table Device Affinity Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_LAR, Core ROM table Software Lock Access Register

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_LSR, Core ROM table Software Lock Status Register

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_AUTHSTATUS, Core ROM table Authentication Status Register

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_DEVARCH, Core ROM table Device Architecture Register

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_DEVID2, Core ROM table Device Configuration Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_DEVID1, Core ROM table Device Configuration Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_DEVID, Core ROM table Device Configuration Register

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_DEVTYPE, Core ROM table Device Type Register

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_PIDR4, Core ROM table Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_PIDR5, Core ROM table Peripheral Identification Register 5

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_PIDR6, Core ROM table Peripheral Identification Register 6

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_PIDR7, Core ROM table Peripheral Identification Register 7

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_PIDR0, Core ROM table Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_PIDR1, Core ROM table Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_PIDR2, Core ROM table Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_PIDR3, Core ROM table Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_CIDR0, Core ROM table Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_CIDR1, Core ROM table Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_CIDR2, Core ROM table Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
COREROM_CIDR3, Core ROM table Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIINTACK, CTI Output Trigger Acknowledge register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIAPPSET, CTI Application Trigger Set register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIAPPCLEAR, CTI Application Trigger Clear register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIAPPPULSE, CTI Application Pulse register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIINEN<n>, CTI Input Trigger to Output Channel Enable registers, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIOUTEN<n>, CTI Input Channel to Output Trigger Enable registers, n = 0 - 9

# topic.topics[].topics[].topics[].topics[].topics[].label
CTITRIGINSTATUS, CTI Trigger In Status register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTITRIGOUTSTATUS, CTI Trigger Out Status register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTICHINSTATUS, CTI Channel In Status register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTICHOUTSTATUS, CTI Channel Out Status register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIGATE, CTI Channel Gate Enable register

# topic.topics[].topics[].topics[].topics[].topics[].label
ASICCTL, CTI External Multiplexer Control register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIITCTRL, CTI Integration mode Control register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTICLAIMCLR, CTI Claim Tag Clear register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIDEVAFF0, CTI Device Affinity register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIDEVAFF1, CTI Device Affinity register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIDEVARCH, CTI Device Architecture register

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIPIDR4, CTI Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIPIDR0, CTI Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIPIDR1, CTI Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIPIDR2, CTI Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
CTIPIDR3, CTI Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
CTICIDR0, CTI Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
CTICIDR1, CTI Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
CTICIDR2, CTI Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
CTICIDR3, CTI Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCBBCTLR, Branch Broadcast Control Register

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCVICTLR, ViewInst Main Control Register

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCVDCTLR, ViewData Main Control Register

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCVDSACCTLR, ViewData Include/Exclude Single Address Comparator Control Register

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCVDARCCTLR, ViewData Include/Exclude Address Range Comparator Control Register

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCSEQEVR<n>, Sequencer State Transition Control Register <n> , n = 0 - 2

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCSEQRSTEVR, Sequencer Reset Control Register

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCEXTINSELR, External Input Select Register

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCCNTRLDVR<n>, Counter Reload Value Register <n> , n = 0 - 1

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCCNTCTLR<n>, Counter Control Register <n> , n = 0 - 1

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCCNTVR<n>, Counter Value Register <n> , n = 0 - 1

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCRSCTLR<n>, Resource Selection Control Register <n> , n = 2 - 15

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCSSCCR<n>, Single-shot Comparator Control Register <n> , n = 0 - 1

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCSSCSR<n>, Single-shot Comparator Control Status Register <n> , n = 0 - 1

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCACVR<n>, Address Comparator Value Register <n> , n = 0 - 7

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCACATR<n>, Address Comparator Access Type Register <n> , n = 0 - 7

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCDVCVR<n>, Data Value Comparator Value Register <n> , n = 0 - 1

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCDVCMR<n>, Data Value Comparator Mask Register <n> , n = 0 - 1

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCCIDCVR<n>, Context Identifier Comparator Value Registers <n> , n = 0

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCVMIDCVR<n>, Virtual Context Identifier Comparator Value Register <n> , n = 0

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCCIDCCTLR0, Context Identifier Comparator Control Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCVMIDCCTLR0, Virtual Context Identifier Comparator Control Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCITCTRL, Integration Mode Control Register

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCPIDR4, Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCPIDR5, Peripheral Identification Register 5

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCPIDR6, Peripheral Identification Register 6

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCPIDR7, Peripheral Identification Register 7

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCPIDR0, Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCPIDR1, Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCPIDR2, Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCPIDR3, Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCCIDR0, Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCCIDR1, Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCCIDR2, Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
TRCCIDR3, Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
PMEVCNTR<n>_EL0, Performance Monitors Event Count Registers, n = 0 - 5

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCCNTR_EL0, Performance Monitors Cycle Counter

# topic.topics[].topics[].topics[].topics[].topics[].label
PMEVTYPER<n>_EL0, Performance Monitors Event Type Registers, n = 0 - 5

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCCFILTR_EL0, Performance Monitors Cycle Counter Filter Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCNTENSET_EL0, Performance Monitors Count Enable Set Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCNTENCLR_EL0, Performance Monitors Count Enable Clear Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMINTENSET_EL1, Performance Monitors Interrupt Enable Set Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCR_EL0, Performance Monitors Control Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCEID0, Performance Monitors Common Event Identification register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCEID1, Performance Monitors Common Event Identification register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCEID2, Performance Monitors Common Event Identification register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCEID3, Performance Monitors Common Event Identification register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
PMMIR, Performance Monitors Machine Identification Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMITCTRL, Performance Monitors Integration mode Control register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMDEVAFF0, Performance Monitors Device Affinity register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
PMDEVAFF1, Performance Monitors Device Affinity register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
PMLAR, Performance Monitors Lock Access Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMLSR, Performance Monitors Lock Status Register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMDEVARCH, Performance Monitors Device Architecture register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMDEVID, Performance Monitors Device ID register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMDEVTYPE, Performance Monitors Device Type register

# topic.topics[].topics[].topics[].topics[].topics[].label
PMPIDR4, Performance Monitors Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].topics[].label
PMPIDR0, Performance Monitors Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
PMPIDR1, Performance Monitors Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
PMPIDR2, Performance Monitors Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
PMPIDR3, Performance Monitors Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCIDR0, Performance Monitors Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCIDR1, Performance Monitors Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCIDR2, Performance Monitors Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].topics[].label
PMCIDR3, Performance Monitors Component Identification Register 3

# topic.topics[].topics[].label
CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values

# topic.topics[].topics[].label
CONSTRAINED UNPREDICTABLE behavior due to inadequate context synchronization

# topic.topics[].topics[].label
Translation table base address alignment

# topic.topics[].topics[].topics[].label
CONSTRAINED UNPREDICTABLE accesses to PMXEVTYPER_EL0 or PMXEVETYPER_EL0

# topic.topics[].topics[].topics[].label
CONSTRAINED UNPREDICTABLE accesses to PMEVCNTR<n>_EL0 and PMEVTYPER<n>_EL0

# topic.topics[].topics[].topics[].label
CONSTRAINED UNPREDICTABLE behavior caused by MDCR_EL2.HPMN

# topic.topics[].topics[].label
Syndrome register handling for CONSTRAINED UNPREDICTABLE instructions treated as UNDEFINED

# topic.topics[].topics[].label
Mapping of non-idempotent memory locations using the Normal memory type

# topic.topics[].topics[].label
Programming the CSSELR_EL1.Level for a cache level that is not implemented

# topic.topics[].topics[].label
Crossing a page boundary with different memory types or Shareability attributes

# topic.topics[].topics[].topics[].label
LDR (immediate), LDRB (immediate), LDRH (immediate), LDRSB (immediate), LDRSH (immediate), LDRSW (immediate)

# topic.topics[].topics[].topics[].label
STR (immediate), STRB (immediate), STRH (immediate)

# topic.topics[].topics[].label
Out of range values of the Set/Way/Index fields in cache maintenance instructions

# topic.topics[].topics[].label
Reserved values in System and memory-mapped registers and translation table entries

# topic.topics[].topics[].label
CONSTRAINED UNPREDICTABLE behavior in Debug state

# topic.topics[].topics[].topics[].label
Instructions that are CONSTRAINED UNPREDICTABLE in Debug state

# topic.topics[].topics[].topics[].label
Changing the value of EDECR.SS when not in Debug state

# topic.topics[].topics[].topics[].label
External debug interface accesses to registers in reset

# topic.topics[].topics[].topics[].label
External accesses to DBGBVR<n>_EL1 and DBGBCR<n>_EL1

# topic.topics[].topics[].topics[].label
External accesses to DBGWVR<n>_EL1 and DBGWCR<n>_EL1

# metadata.contentDescription
This manual is for the Cortex -R82 processor. It provides reference information and contains programming details for registers. It also describes the memory system, the interrupts, the debug features, and other key features of the processor.