# title
Arm Corstone SSE-710 Subsystem Technical Reference Manual

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Arm® Corstone™ SSE-710 Subsystem Technical Reference Manual

# topic.topics[].topics[].topics[].label
Host CPU Debug APB (HOSTCPUDBG) interface

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Host CPU CTI Channel In (HOSTCPUCTICHIN) interface

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Host CPU CTI Channel Out (HOSTCPUCTICHOUT) interface

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Host CPU Debug Authentication (HOSTCPUDBGAUTH) interface

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Host CPU Power Control (HOSTCPUPWR) interface

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Host CPU Configuration (HOSTCPUCFG) interface

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Host System Generic Timestamp Gray (HOSTCNTVALUEG) interface

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GIC Shared Interrupt (GICSHDINT) interface

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External System {0-1} Reset Output interface

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External System {0-1} Reset Input interface

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External System {0-1} Memory (EXTSYS{0-1}MEM) interface

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External System {0-1} MHU (EXTSYS{0-1}MHU) interface

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External System {0-1} MHU Interrupt (EXTSYS{0-1}MHUINT) interface

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External System {0-1} Trace Expansion (EXTSYS{0-1}TRACEEXP) interface

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External System {0-1} Debug APB (EXTSYS{0-1}DBG) interface

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External System {0-1} External Debug APB (EXTSYS{0-1}EXTDBG) interface

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External System {0-1} CTI Channel In (EXTSYS{0-1}CTICHIN) interface

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External System {0-1} CTI Channel Out (EXTSYS{0-1}CTICHOUT) interface

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External System {0-1} Shared Interrupt (EXTSYS{0-1}SHDINT) interface

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External System {0-1} Memory Clock Q-Channel (EXTSYS{0-1}ACLKQ) interface

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External System {0-1} MHU Clock Q-Channel (EXTSYS{0-1}MHUCLKQ) interface

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External System {0-1} Trace Clock Q-Channel (EXTSYS{0-1}ATCLKQ) interface

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External System {0-1} Debug Master Clock Q-Channel (EXTSYS{0-1}DBGCLKMQ) interface

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External System {0-1} Debug Slave Clock Q-Channel (EXTSYS{0-1}DBGCLKSQ) interface

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External System {0-1} CTI Clock Q-Channel (EXTSYS{0-1}CTICLKQ) interface

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External System {0-1} Memory Power Q-Channel (EXTSYS{0-1}MEMPWRQ) interface

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External System {0-1} MHU Power Q-Channel (EXTSYS{0-1}MHUPWRQ) interface

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External System {0-1} MHU Power Request (EXTSYS{0-1}MHUPWRREQ) interface

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External System {0-1} Trace Expansion Power Q-Channel (EXTSYS{0-1}TRACEEXPPWRQ) interface

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External System {0-1} Debug APB Power Q-Channel (EXTSYS{0-1}DBGPWRQ) interface

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External System {0-1} External Debug APB Power Q-Channel (EXTSYS{0-1}EXTDBGPWRQ) interface

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External System {0-1} CTI In Power Q-Channel (EXTSYS{0-1}CTIINPWRQ) interface

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External System {0-1} CTI Out Power Q-Channel (EXTSYS{0-1}CTIOUTPWRQ) Interface

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External System {0-1} DBGTOP Q-Channel (EXTSYS{0-1}DBGTOPQ) interface

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External System {0-1} SYSTOP Q-Channel (EXTSYS{0-1}SYSTOPQ) interface

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External System {0-1} AONTOP Q-Channel (EXTSYS{0-1}AONTOPQ) interface

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External System {0-1} Power Request (EXTSYS{0-1}PWRREQ) interface

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Off-chip Volatile Memory (OCVM) interface

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Host Expansion Slave {0-1} (HOSTEXPSLV{0-1}) interfaces

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Host Expansion Master {0-1} (HOSTEXPMST{0-1}) interfaces

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Host AON Expansion Master (HOSTAONEXPMST) interface

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Host Debug APB Expansion (HOSTDBGEXP) interface

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Host Debug Trace Expansion (HOSTDBGTRACEEXP) interface

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Host CTI Channel In Expansion (HOSTCTICHINEXP) interface

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Host CTI Channel Out Expansion (HOSTCTICHOUTEXP) interface

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Host Debug Timestamp (HOSTTSVALUEB) interface

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Host STM DMA Peripheral Request (HOSTSTMDPR) interface

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Host System REFCLK Generic Timestamp Gray (HOSTCNTVALUEG) interface

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Host System REFCLK Generic Timestamp Binary (HOSTCNTVALUEB) interface

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Host System S32K Timestamp Gray (HOSTS32KCNTVALUEG) interface

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Host System S32K Timestamp Binary (HOSTS32KCNTVALUEB) interface

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Host System Debug Power Request (HOSTDBGPWRREQ) interface

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Host System UART {0,1} (HOSTUART{0,1}) interface

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 Crypto AON Clock (CRYPTOAONCLKOUT) Interface

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Crypto Accelerator Configuration (CAC) interface

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Crypto Accelerator AON (CAAON) interface

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Crypto Accelerator lifecycle Control (CALC) interface

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Crypto Accelerator Interrupt (CAINT) interface

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Crypto Accelerator Power Q-Channel (CAPWRQ) interface

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Crypto Accelerator Error (CAE) interface

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Secure Enclave UART (SECENCUART) interface

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Debug Authorization Access Control Gate (DAACG)

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Reserved address space and error responses

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Cortex-M0+ Private Peripheral Bus (PPB) region

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Host Base System Control register summary

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Cluster Static Config (CLUS_CFG) register

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Processing Element {0-3} Static Config (PE{0-3}_CFG) register

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Processing Element {0-3} Reset Vector Base Address Lower and Upper (PE{0-3}_RVBAR_LW) register

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Processing Element {0-3} Reset Vector Base Address Upper (PE{0-3}_RVBAR_UP) register

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Host Reset Syndrome (HOST_RST_SYN) register

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Host CPU Boot Mask (HOST_CPU_BOOT_MSK) register

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Host CPU Cluster Power Request (HOST_CPU_CLUS_PWR_REQ) register

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Host CPU Wakeup (HOST_CPU_WAKEUP) register

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External System {0-1} Reset Control (EXT_SYS{0-1}_RST_CTRL) register

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External System {0-1} Reset Status (EXT_SYS{0-1}_RST_ST) register

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Base System Power Request (BSYS_PWR_REQ) register

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Base System Power Status (BSYS_PWR_ST) register

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Host System Lock Control Status (HOST_SYS_LCTRL_ST) register

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Host System Lock Control Set (HOST_SYS_LCTRL_SET) register

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Host System Lock Control Clear (HOST_SYS_LCTRL_CLR) register

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Host CPU Clock Control (HOSTCPUCLK_CTRL) register

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Host CPU Clock Divider 0 (HOSTCPUCLK_DIV0) register

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Host CPU Clock Divider 1 (HOSTCPUCLK_DIV1) register

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GIC Clock Control (GICCLK_CTRL) register

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GIC Clock Divider 0 (GICCLK_DIV0) register

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AXI Clock Divider 0 (ACLK_DIV0) register

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Control Clock Control (CTRLCLK_CTRL) register

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Control Clock Divider 0 (CTRLCLK_DIV0) register

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Debug Clock Control (DBGCLK_CTRL) register

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Debug Clock Divider 0 (DBGCLK_DIV0) register

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Host UART Clock Control (HOSTUARTCLK_CTRL) register

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Host UART Clock Divider 0 (HOSTUARTCLK_DIV0) register

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Clock Force Status (CLKFORCE_ST) register

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Clock Force Clear (CLKFORCE_CLR) register

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Host PPU Interrupt Status (HOST_PPU_INT_ST) register

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Secure Enclave Base System Control register summary

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Host System Reset Control (HOST_SYS_RST_CTRL) register

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Host System Reset Status (HOST_SYS_RST_ST) register

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SoC Reset Control (SOC_RST_CTRL) register

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Secure Enclave Interrupt Collator Status 0 (SEC_ENC_INT_COL_ST0) register

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Secure Enclave Interrupt Collator Status 1 (SEC_ENC_INT_COL_ST1) register

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Secure Enclave Interrupt Collator Status 2 (SEC_ENC_INT_COL_ST2) register

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Secure Enclave Interrupt Collator Status 3 (SEC_ENC_INT_COL_ST3) register

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Secure Enclave Interrupt Collator Mask 0 (SEC_ENC_INT_COL_MSK0) register

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Secure Enclave Interrupt Collator Mask 1 (SEC_ENC_INT_COL_MSK1) register

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Secure Enclave Interrupt Collator Mask 2 (SEC_ENC_INT_COL_MSK2) register

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Secure Enclave Interrupt Collator Mask 3 (SEC_ENC_INT_COL_MSK3) register

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Base System Power Request (BSYS_PWR_REQ) register

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Base System Power Status (BSYS_PWR_ST) register

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SECENCCLK Clock Divider (SECENCCLK_DIV) register

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Clock Force Status (CLKFORCE_ST) register

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Clock Force Clear (CLKFORCE_CLR) register

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Secure Enclave Phase Locked Loop (PLL) Status (SEC_ENC_PLL_ST) register

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SoC Reset Syndrome (SOC_RST_SYN) register

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Secure Enclave System Control register summary

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Secure Enclave Reset Syndrome (SE_RST_SYN) register

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Secure Enclave Reset Mask (SE_RST_MSK) register

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Secure Enclave Power Control (SE_PWR_CTRL) register

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Secure Enclave General Purpose {0-3} (SE_GP{0-3}) register

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Secure Enclave Clock Divider Control (SE_CLK_DIV) register

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Secure Enclave Build Configuration (SE_BLD_CFG) register

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Interrupt Router Control (INT_RTR_CTRL) register

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Shared Interrupt Lock Control (SHD_INT_LCTRL) register

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Shared Interrupt Select (SHD_INT_SEL) register

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Interrupt Router Tamper Status (INT_RTR_TMP_ST) register

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REFCLK Counter CNTControl register summary

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CNTControl Counter Synchronization Control (CNTSCR) register

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CNTControl Synchronized Counter Value (CNTSVL) register

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CNTControl Synchronized Counter Value (CNTSVU) register

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Base System Config 0 (BSYS_CFG0) register

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Base System Config 1 (BSYS_CFG1) register

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Base System Config 2 (BSYS_CFG2) register

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Base System Config 3 (BSYS_CFG3) register

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Boot Instruction Register {0-3} (BIR{0-3})

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Boot Instruction Register {4-15} (BIR{4-15})

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General Purpose Output {0-31} Control (GPO{0-31}_CTRL) register

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General Purpose Input {0-31} Status (GPI{0-31}_ST) register

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Device Configuration 2 (DEVID2) register

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Device Configuration 1 (DEVID1) register

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Device Type Identifier (DEVTYPE) register

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Host and External System {0-1} reset request

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CH_ST_MSK, Channel Status Masked register

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CH_INT_ST, Channel Interrupt Status register

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CH_INT_CLR, Channel Interrupt Clear register

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CH_INT_EN, Channel Interrupt Enable register

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MHU_CFG, Message Handling Unit Configuration register

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CHCOMB_INT_STn, Channel Combined Interrupt Status registers, n = 0–3

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Software configuration of the Interrupt Router

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Accesses to locked interrupt configurations

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Bus Slave incoming transaction properties rules

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Bus Master output transactions properties rules

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Firewall Component Capability Register 0 (FC_CAP0)

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Firewall Component Capability Register 2 (FC_CAP2)

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Firewall Component Capability Register 3 (FC_CAP3)

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Firewall Component Configuration Register 0 (FC_CFG0)

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Firewall Component Configuration Register 1 (FC_CFG1)

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Firewall Component Configuration Register 2 (FC_CFG2)

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Firewall Component Configuration Register 3 (FC_CFG3)

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Region Translation Config {0,1} (RGN_TCFG{0,1})

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Region Master Permission List {0-3} (RGN_MPL{0-3})

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Fault Entry Transaction Address Lower (FE_TAL)

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Fault Entry Transaction Address Upper (FE_TAU)

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Fault Entry Transaction Properties (FE_TP)

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Changing Configuration Settings of Protection Logic

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Enabling and disabling the Firewall Component’s protection logic

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Changing terminated transaction response type

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Changing terminated transaction read data response

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Protection logic terminated transaction response

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Error Detection Report Transaction Address Lower (EDR_TAL)

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Error Detection Report Transaction Address Upper (EDR_TAU)

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Error Detection Transaction Properties (EDR_TP)

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Error Detection Report MasterID (EDR_MID)

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Error Detection Report Control (EDR_CTRL)

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Changing configuration settings of monitor logic

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Changing error detection report power behavior

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Changing error transaction read data response

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Output transaction memory attribute property

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Output transaction privilege level property

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Address translation and protection extension level

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Changing lockdown state of Firewall Component and regions

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 Register Behavior when SRE.0 Implemented

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Register Behavior when SRE.1 Implemented

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Firewall Tamper Transaction Address (FW_TMP_TA) 

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Firewall Shadow Register Control (FW_SR_CTRL) register

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Firewall Component {0-31} Interrupt Status (FC{0-31}_INT_ST) register

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Firewall Interrupt Status (FW_INT_ST) register

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Firewall Component {0-31} Interrupt Mask (FC{0-31}_INT_MSK) register

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Changing Configurations Settings of Firewall

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Changing Configuration Access Error Response Type

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Changing Configuration Access Error Read Data Response

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Update region address range or translation

# metadata.contentDescription
This book is for the Arm® Corstone™ SSE-710 Subsystem..