# title
Arm Neoverse N2 reference design Technical Overview

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Arm® Neoverse™ N2 reference design Technical Overview

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Overview of Neoverse N2 reference design

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GIC Interrupt Translation Service options

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I/O Virtualization block voltage domains

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PD_CPUn power domain power control sequences

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PD_CPUn power sequence from the OFF to the ON state

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PD_CPUn power sequence from the ON to the OFF state

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I/O coherent expansion slave interfaces (EXSACEL<0-n>, EXSACELD<0-n>)

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I/O coherent expansion slave interfaces with integrated inline TBUs (EXSACELT<0-n>)

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GIC expansion interrupts interface (EXGICINT)

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LTI expansion slave interfaces (EXSLTI<0-n>)

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ATS_DTI expansion slave interfaces (EXSATS<0-n>)

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MSI expansion slave interfaces (EXSMSI<0-n>)

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STM event expansion interfaces (EXSSTME<0-n>)

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CoreSight ATB slave trace expansion interfaces (EXSATB<0-n>)

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CoreSight APB master expansion interface (EXMDBGAPB)

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CoreSight Cross Trigger Interface (EXCTM)

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AMBA CXS expansion master and slave interfaces (EXSCXSB<0-n>, EXMCXSB<0-n>)

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SCP PIK expansion interfaces (EXSCPPIK<0-n>)

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AP, SCP, and MCP UART interfaces (APNSUART, APSUART, SCPUART, MCPUART)

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Generic timer synchronization between the chips

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Interconnect block NIC-450 GPV memory map

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SID_SYSTEM_ID, System ID System Identification register

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SID_SOC_ID, System ID SoC Identification register

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SID_CHIP_ID, System ID Chip Identification register

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SID_SYSTEM_CFG, System ID System Configuration register

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SID PID_4, System ID Peripheral ID 4 register

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SID PID_0, System ID Peripheral ID 0 register

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SID PID_1, System ID Peripheral ID 1 register

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SID PID_2, System ID Peripheral ID 2 register

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SID PID_3, System ID Peripheral ID 3 register

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COMPID0, System ID Component ID 0 register

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COMPID1, System ID Component ID 1 register

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COMPID2, System ID Component ID 2 register

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COMPID3, System ID Component ID 3 register

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CNTENCR, Counter Enable Control register

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CNTSAMPVAL_L, Counter Sample Counter Lower Value register

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CNTSAMPVAL_U, Counter Sample Counter Upper Value register

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CNTINCR, Counter Increment Control register

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CNTControl PID_4, CNTControl Peripheral ID 4 register

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CNTControl PID_0, CNTControl Peripheral ID 0 register

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CNTControl PID_1, CNTControl Peripheral ID 1 register

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CNTControl PID_2, CNTControl Peripheral ID 2 register

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CNTControl PID_3, CNTControl Peripheral ID 3 register

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COMPID0, CNTControl Component ID 0 register

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COMPID1, CNTControl Component ID 1 register

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COMPID2, CNTControl Component ID 2 register

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COMPID3, CNTControl Component ID 3 register

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CNTReadBase PID_4, CNTReadBase Peripheral ID 4 register

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CNTReadBase PID_0, CNTReadBase Peripheral ID 0 register

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CNTReadBase PID_1, CNTReadBase Peripheral ID 1 register

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CNTReadBase PID_2, CNTReadBase Peripheral ID 2 register

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CNTReadBase PID_3, CNTReadBase Peripheral ID 3 register

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COMPID0, CNTReadBase Component ID 0 register

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COMPID1, CNTReadBase Component ID 1 register

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COMPID2, CNTReadBase Component ID 2 register

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COMPID3, CNTReadBase Component ID 3 register

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CNTPIDR4, Timer Control Peripheral ID 4 register

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CNTPIDR0, Timer Control Peripheral ID 0 register

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CNTPIDR1, Timer Control Peripheral ID 1 register

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CNTPIDR2, Timer Control Peripheral ID 2 register

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CNTPIDR3, Timer Control Peripheral ID 3 register

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CNTCIDR0, Timer Control Component ID 0 register

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CNTCIDR1, Timer Control Component ID 1 register

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CNTCIDR2, Timer Control Component ID 2 register

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CNTCIDR3, Timer Control Component ID 3 register

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CNTPIDR4, Timer Peripheral ID 4 register

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CNTPIDR0, Timer Peripheral ID 0 register

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CNTPIDR1, Timer Peripheral ID 1 register

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CNTPIDR2, Timer Peripheral ID 2 register

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CNTPIDR3, Timer Peripheral ID 3 register

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System generic timer synchronization registers

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SLVCHIP_GCNT_INT_STATUS, Slave Generic Counter Interrupt Status register

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GCNT_TIMEOUT, Generic Counter Timeout register

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SLVCHIP_GCNT_UPDT_VAL_L, Slave Generic Counter Update Lower Value register

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SLVCHIP_GCNT_UPDT_VAL_U, Slave Generic Counter Update Upper Value register

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SLVCHIP_GCNT_NW_DLY, Slave Generic Counter Network Delay register

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SLVCHIP_GCNT_RETRY_CNT, Slave Generic Counter Retry Count register

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SLVCHIP_GCNT_MSTSLV_DIFF_L, Slave Generic Counter Time value difference (Lower 32 bits)

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SLVCHIP_GCNT_MSTSLV_DIFF_U, Slave Generic Counter Time value difference (Upper 32 bits)

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PID_4, Generic Counter Synchronization Peripheral ID 4 register

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PID_0, Generic Counter Synchronization Peripheral ID 0 register

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PID_1, Generic Counter Synchronization Peripheral ID 1 register

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PID_2, Generic Counter Synchronization Peripheral ID 2 register

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PID_3, Generic Counter Synchronization Peripheral ID 3 register

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COMP_ID0, Generic Counter Synchronization Component ID 0 register

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COMP_ID1, Generic Counter Synchronization Component ID 1 register

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COMP_ID2, Generic Counter Synchronization Component ID 2 register

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COMP_ID3, Generic Counter Synchronization Component ID 3 register

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Application Processor Watchdog timer registers

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IIDR, AP Watchdog Control Interface Identification Register

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PID4, AP Watchdog Control Peripheral ID 4 register

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PID0, AP Watchdog Control Peripheral ID 0 register

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PID1, AP Watchdog Control Peripheral ID 1 register

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PID2, AP Watchdog Control Peripheral ID 2 register

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PID3, AP Watchdog Control Peripheral ID 3 register

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COMPID0, AP Watchdog Control Component ID 0 register

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COMPID1, AP Watchdog Control Component ID 1 register

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COMPID2, AP Watchdog Control Component ID 2 register

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COMPID3, AP Watchdog Control Component ID 3 register

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IIDR, AP Watchdog Refresh Interface Identification Register

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PID4, AP Watchdog Refresh Peripheral ID 4 register

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PID0, AP Watchdog Refresh Peripheral ID 0 register

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PID1, AP Watchdog Refresh Peripheral ID 1 register

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PID2, AP Watchdog Refresh Peripheral ID 2 register

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PID3, AP Watchdog Refresh Peripheral ID 3 register

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COMPID0, AP Watchdog Refresh Component ID 0 register

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COMPID1, AP Watchdog Refresh Component ID 1 register

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COMPID2, AP Watchdog Refresh Component ID 2 register

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COMPID3, AP Watchdog Refresh Component ID 3 register

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RAMECC_ERRADDR, Secure SRAM error address

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PID4, Base SRAM ECC Peripheral ID 4 register

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PID0, Base SRAM ECC Peripheral ID 0 register

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PID1, Base SRAM ECC Peripheral ID 1 register

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PID2, Base SRAM ECC Peripheral ID 2 register

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PID3, Base SRAM ECC Peripheral ID 3 register

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COMPID0, Base SRAM ECC Component ID 0 register

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COMPID1, Base SRAM ECC Component ID 1 register

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COMPID2, Base SRAM ECC Component ID 2 register

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COMPID3, Base SRAM ECC Component ID 3 register

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CH_ST_MSK, MHU Channel Status Masked register

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CH_MSK_ST, MHU Channel Mask Status register

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CH_MSK_SET, MHU Channel Mask Set register

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CH_MSK_CLR, MHU Channel Mask Clear register

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MHU_CFG, Message Handling Unit Configuration register

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RESP_CFG, MHU Response Configuration register

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ACCESS_REQUEST, MHU Access Request register

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INT_ST, MHU Sender Interrupt Status register

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INT_CLR, MHU Sender Interrupt Clear register

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INT_EN, MHU Sender Interrupt Enable register

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INT_ST, MHU Receiver Interrupt Status register

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INT_CLR, MHU Receiver Interrupt Clear register

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INT_EN, MHU Receiver Interrupt Enable register

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CHCOMB_INT_ST<0-3>, MHU Sender Channel Combined Interrupt Status 0-3 register

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CHCOMB_INT_ST<0-3>, MHU Receiver Channel Combined Interrupt Status 0-3 register

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IIDR, MHU Implementer Identification Register

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AIDR, MHU Architecture Identification Register

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Core Manager and clock control registers

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PE_RVBARADDR_LW, Processing Element Reset Vector Base Address Lower Word register

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PE_RVBARADDR_UP, Processing Element Reset Vector Base Address Upper Word register

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PE_STATUS, Core PMU signal status register

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CLUS_PPUCLK_CTRL, Cluster PPU Clock Control register

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CLUS_PPUCLK_DIV1, Cluster PPU Clock Divider Control register

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CLUS_GICCLK_CTRL, Cluster GIC Clock Control register

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CLUS_GICCLK_DIV1, Cluster GIC Clock Divider Control register

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CLUS_PERIPHCLK_DIV1, Cluster Peripheral Clock Divider Control register

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CORE_CLK_CTRL, Core Clock Control register

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CORECLK_DIV1, Core Clock Divider Control register

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CORECLK_MOD1, Core- and Complex Clock Modulator Control register

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CLKFORCE_STATUS, Clock Force Status register

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CLKFORCE_CLR, Clock Force Clear register

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PID4, Power Control Peripheral ID 4 register

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PID5, Power Control Peripheral ID 5 register

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PID6, Power Control Peripheral ID 6 register

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PID7, Power Control Peripheral ID 7 register

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PID0, Power Control Peripheral ID 0 register

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PID1, Power Control Peripheral ID 1 register

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PID2, Power Control Peripheral ID 2 register

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PID3, Power Control Peripheral ID 3 register

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ID0, Power Control Component ID 0 register

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ID1, Power Control Component ID 1 register

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ID2, Power Control Component ID 2 register

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ID3, Power Control Component ID 3 register

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INTCLK_CTRL, Cache Coherent Interconnect Clock Control register

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INTCLK_DIV1, Cache Coherent Interconnect Clock Divider Control register

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GICCLK_DIV1, GIC Clock Divider Control register

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SCPPIKCLK_CTRL, SCP APB Clock Control register

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SCPPIKCLK_DIV1, SCP APB Clock Divider Control register

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SYSPERCLK_CTRL, System Peripheral Clock Control register

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SYSPERCLK_DIV1, System Peripheral Clock Divider Control register

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DMCCLK_DIV1, DMC Clock Divider Control register

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APUARTCLK_CTRL, UART Clock Control register

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APUARTCLK_DIV1, UART Clock Divider Control register

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IONCICLK_CTRL, I/O NCI Network Clock Control register

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IONCICLK_DIV1, I/O NCI Network Clock Divider Control register

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TCU<x>CLK_CTRL, TCU Clock Control register

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TCU<x>CLK_DIV1, TCU Clock Divider Control register

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TCUx_CLK_ENABLE, TCU Clock Enable register

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NCIx_CLK_ENABLE, NCI Clock Enable register

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CLKFORCE_STATUS, System PIK Clock Force Status register

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CLKFORCE_SET, System PIK Clock Force Set register

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CLKFORCE_CLR, System PIK Clock Force Clear register

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PIK_CONFIG, System PIK Configuration register

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PID4, System PIK Peripheral ID 4 register

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PID5, System PIK Peripheral ID 5 register

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PID6, System PIK Peripheral ID 6 register

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PID7, System PIK Peripheral ID 7 register

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PID0, System PIK Peripheral ID 0 register

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PID1, System PIK Peripheral ID 1 register

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PID2, System PIK Peripheral ID 2 register

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PID3, System PIK Peripheral ID 3 register

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DBG_PWR_REQ_ST, Debug Power Request Status register

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DBG_PWR_ACK, Debug Power Request Acknowledge register

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DBG_RST_REQ_ST, Debug Reset Request Status register

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DBG_RST_ACK, Debug Reset Request Acknowledge register

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SYS_PWR_REQ_ST, System Power-up Request Status register

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SYS_PWR_ACK, System Power-up Request Acknowledge register

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SYS_RST_REQ_ST, System Reset Request Status register

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SYS_RST_ACK, System Reset Request Acknowledge register

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TRACECLK_CTRL, TPIU Clock Control register

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TRACECLK_DIV1, TPIU Clock Divider Control register

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SYSDBGPCLK_CTRL, Debug APB Clock Control register

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SYSDBGPCLK_DIV1, Debug APB Clock Divider register

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DBGCLK_CTRL, CoreSight ATB Input Expansion Clock Control register

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DBGCLK_DIV1, CoreSight ATB Input Expansion Clock Divider register

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CLKFORCE_STATUS, Debug PIK Clock Force Status register

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CLKFORCE_SET, Debug PIK Clock Force Set register

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CLKFORCE_CLR, Debug PIK Clock Force Clear register

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DBG_PWR_REQ_INT_ST, Debug Power Request Interrupt Status register

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DBG_RST_REQ_INT_ST, Debug Reset Request Interrupt Status register

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SYS_PWR_REQ_INT_ST, System Power Request Interrupt Status register

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SYS_RST_REQ_INT_ST, System Reset Request Interrupt Status register

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DAP_TARGET_ID, Debug Access Port Target ID register

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DAP_INSTANCE_ID, Debug Access Port Instance ID register

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PCL_CFG, Power Control Logic Configuration register

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PID4, Debug PIK Peripheral ID 4 register

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PID5, Debug PIK Peripheral ID 5 register

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PID6, Debug PIK Peripheral ID 6 register

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PID7, Debug PIK Peripheral ID 7 register

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PID0, Debug PIK Peripheral ID 0 register

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PID1, Debug PIK Peripheral ID 1 register

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PID2, Debug PIK Peripheral ID 2 register

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PID3, Debug PIK Peripheral ID 3 register

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Debug Chain Power Control Logic registers

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DBG_CHN_PWR_REQ_ST, Debug Chain Power Request Status register

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DBG_CHN_PWR_ACK, Debug Chain Power Request Acknowledge register

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DBG_CHN_PPU_INT_ST, Debug Chain PPU Interrupt Status register

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DBG_CHN_PWRUP_INT_ST, Debug Chain Power-up Interrupt Status register

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PCL_CFG, Power Control Logic Configuration register

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PID4, Debug Chain Power Control Peripheral ID 4 register

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PID5, Debug Chain Power Control Peripheral ID 5 register

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PID6, Debug Chain Power Control Peripheral ID 6 register

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PID7, Debug Chain Power Control Peripheral ID 7 register

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PID0, Debug Chain Power Control Peripheral ID 0 register

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PID1, Debug Chain Power Control Peripheral ID 1 register

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PID2, Debug Chain Power Control Peripheral ID 2 register

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PID3, Debug Chain Power Control Peripheral ID 3 register

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ID0, Debug Chain Power Control Component ID 0 register

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ID1, Debug Chain Power Control Component ID 1 register

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ID2, Debug Chain Power Control Component ID 2 register

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ID3, Debug Chain Power Control Component ID 3 register

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ADDR_TRANS, MSCP Address Translation register

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DBG_ADDR_TRANS, MSCP AP Debug Address Translation register

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WS1_TIMER_MATCH, WS1 Timer Value register

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SS_RESET_SET, Subsystem Reset Request Set register

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CORECLK_CTRL, Core Clock Control register

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CORECLK_DIV1, Core Clock Divider register

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GTSYNCCLK_CTRL, Generic Timer Synchronization Clock Control register

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GTSYNCCLK_DIV1, Generic Timer Synchronization Clock Divider Control register

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CLKFORCE_STATUS, Clock Force Status register

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CLKFORCE_CLR, MSCP PWR CTRL Clock Force Clear register

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CONS_MMUTCU_INT_STATUS, Consolidated MMU TCU Interrupt Status register

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CONS_MMUTCU_INT_CLR, Consolidated MMU TCU Interrupt Clear register

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CONS_MMUTBU_INT_STATUS0, Consolidated MMU TBU RAS FHI Interrupt Status register

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CONS_MMUTBU_INT_CLR0, Consolidated MMU TBU RAS FHI Interrupt Clear register

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CONS_MMUTBU_INT_STATUS1, Consolidated MMU TBU32-TBU63 RAS FHI Interrupt Status register

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CONS_MMUTBU_INT_CLR1, Consolidated MMU TBU32-TBU63 RAS FHI Interrupt Clear register

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CONS_MMUTBU_INT_STATUS2, Consolidated MMU TBU RAS ERI Interrupt Status register

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CONS_MMUTBU_INT_CLR2, Consolidated MMU TBU RAS ERI Interrupt Clear register

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CONS_MMUTBU_INT_STATUS3, Consolidated MMU TBU32-TBU63 RAS ERI Interrupt Status register

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CONS_MMUTBU_INT_CLR3, Consolidated MMU TBU32-TBU63 RAS ERI Interrupt Clear register

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CONS_MMUTBU_INT_STATUS4, Consolidated MMU TBU RAS CRI Interrupt Status register

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CONS_MMUTBU_INT_CLR4, Consolidated MMU TBU RAS CRI Interrupt Clear register

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CONS_MMUTBU_INT_STATUS5, Consolidated MMU TBU32-TBU63 RAS CRI Interrupt Status register

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CONS_MMUTBU_INT_CLR5, Consolidated MMU TBU32-TBU63 RAS CRI Interrupt Clear register

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CPU_PPU_INT_STATUS<x>, CPU PPU Interrupt Status register, x = 0-3

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CLUS_PPU_INT_STATUS<x>, Cluster PPU Interrupt Status register, x = 0-3

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CPU_PLL_LOCK_STATUS<x>, CPU PLL Lock Status register, x = 0-7

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CPU_PLL_UNLOCK_STATUS<x>, CPU PLL Unlock Status register, x = 0-7

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CONS_CLUS_SCF_INT_STATUS<x>, Cluster SCF Interrupt Status register, x = 0-7

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TCMECC_ERRSTATUS, TCM ECC Error Status register

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TCMECC_ERRCTRL, TCM ECC Error Control register

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TCMECC_ERRCODE, TCM ECC Error Code register

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TCMECC_ERRADDR, TCM ECC Error Address register

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PWR_CTRL_CONFIG, MSCP Power Control Configuration register

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PERIPHERAL_ID4, MSCP Power Control Peripheral ID 4 register

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PERIPHERAL_ID5, MSCP Power Control Peripheral ID 5 register

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PERIPHERAL_ID6, MSCP Power Control Peripheral ID 6 register

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PERIPHERAL_ID7, MSCP Power Control Peripheral ID 7 register

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PERIPHERAL_ID0, MSCP Power Control Peripheral ID 0 register

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PERIPHERAL_ID1, MSCP Power Control Peripheral ID 1 register

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PERIPHERAL_ID2, MSCP Power Control Peripheral ID 2 register

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PERIPHERAL_ID3, MSCP Power Control Peripheral ID 3 register

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COMPONENT_ID0, MSCP Power Control Component ID 0 register

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COMPONENT_ID1, MSCP Power Control Component ID 1 register

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COMPONENT_ID2, MSCP Power Control Component ID 2 register

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COMPONENT_ID3, MSCP Power Control Component ID 3 register

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DMC_MISC_CONTROL, DMC TZC Bypass and Address Decode Control register

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DMC_RAWERR_INT_STATUS, DMC Error Interrupt Status register

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PCIe_CTRL_x4_0_ECAM1_START_ADDR, x4 CTRL0 ECAM Start Address register

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PCIe_CTRL_x4_0_ECAM1_END_ADDR, x4 CTRL0 ECAM End Address register

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PCIe_CTRL_x4_0_MMIOL_START_ADDR, x4 CTRL0 MMIOL Start Address register

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PCIe_CTRL_x4_0_MMIOL_END_ADDR, x4 CTRL0 MMIOL End Address register

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PCIe_CTRL_x4_0_MMIOH_START_ADDR, x4 CTRL0 MMIOH Start Address register

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PCIe_CTRL_x4_0_MMIOH_END_ADDR, x4 CTRL0 MMIOH End Address register

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PCIe_CTRL_x4_0_MMIOH2L_TR_START_ADDR, x4 CTRL0 MMIOH2L Translated Region Start Address register

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PCIe_CTRL_x4_0_MMIOH2L_TR_END_ADDR, x4 CTRL0 MMIOH2L Translated Region End Address register

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PCIe_CTRL_x4_0_CFG_END_ADDR, x4 CTRL0 Configuration End Address register

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PCIe_CTRL_x4_0_ECAM2_START_ADDR, x4 CTRL0 ECAM2 Start Address register

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PCIe_CTRL_x4_0_ECAM2_END_ADDR, x4 CTRL0 ECAM2 End Address register

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PCIe_CTRL_x4_0_ECAM2_ADDR_CTRL, x4 CTRL0 ECAM2 Address Control register

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PCIe_CTRL_x4_1_ECAM1_START_ADDR, x4 CTRL1 ECAM Start Address register

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PCIe_CTRL_x4_1_ECAM1_END_ADDR, x4 CTRL1 ECAM End Address register

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PCIe_CTRL_x4_1_MMIOL_START_ADDR, x4 CTRL1 MMIOL Start Address register

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PCIe_CTRL_x4_1_MMIOL_END_ADDR, x4 CTRL1 MMIOL End Address register

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PCIe_CTRL_x4_1_MMIOH_START_ADDR, x4 CTRL1 MMIOH Start Address register

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PCIe_CTRL_x4_1_MMIOH_END_ADDR, x4 CTRL1 MMIOH End Address register

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PCIe_CTRL_x4_1_MMIOH2L_TR_START_ADDR, x4 CTRL1 MMIOH2L Translated Region Start Address register

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PCIe_CTRL_x4_1_MMIOH2L_TR_END_ADDR, x4 CTRL1 MMIOH2L Translated Region End Address register

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PCIe_CTRL_x4_1_CFG_END_ADDR, x4 CTRL1 Configuration End Address register

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PCIe_CTRL_x4_1_ECAM2_START_ADDR, x4 CTRL1 ECAM2 Start Address register

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PCIe_CTRL_x4_1_ECAM2_END_ADDR, x4 CTRL1 ECAM2 End Address register

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PCIe_CTRL_x4_1_ECAM2_ADDR_CTRL, x4 CTRL1 ECAM2 Address Control register

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PCIe_CTRL_x8_ECAM1_START_ADDR, x8 CTRL ECAM1 Start Address register

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PCIe_CTRL_x8_ECAM1_END_ADDR, x8 CTRL ECAM End Address register

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PCIe_CTRL_x8_MMIOL_START_ADDR, x8 CTRL MMIOL Start Address register

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PCIe_CTRL_x8_MMIOL_END_ADDR, x8 CTRL MMIOL End Address register

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PCIe_CTRL_x8_MMIOH_START_ADDR, x8 CTRL MMIOH Start Address register

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PCIe_CTRL_x8_MMIOH_END_ADDR, x8 CTRL MMIOH End Address register

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PCIe_CTRL_x8_MMIOH2L_TR_START_ADDR, x8 CTRL MMIOH2L Translated Region Start Address register

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PCIe_CTRL_x8_MMIOH2L_TR_END_ADDR, x8 CTRL MMIOH2L Translated Region End Address register

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PCIe_CTRL_x8_CFG_END_ADDR, x8 CTRL Configuration End Address register

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PCIe_CTRL_x8_ECAM2_START_ADDR, x8 CTRL ECAM2 Start Address register

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PCIe_CTRL_x8_ECAM2_END_ADDR, x8 CTRL ECAM2 End Address register

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PCIe_CTRL_x8_ECAM2_ADDR_CTRL, x8 CTRL ECAM2 Address Control register

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PCIe_CTRL_x16_ECAM1_START_ADDR, x16 CTRL ECAM1 Start Address register

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PCIe_CTRL_x16_ECAM1_END_ADDR, x16 CTRL ECAM End Address register

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PCIe_CTRL_x16_MMIOL_START_ADDR, x16 CTRL MMIOL Start Address register

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PCIe_CTRL_x16_MMIOL_END_ADDR, x16 CTRL MMIOL End Address register

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PCIe_CTRL_x16_MMIOH_START_ADDR, x16 CTRL MMIOH Start Address register

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PCIe_CTRL_x16_MMIOH_END_ADDR, x16 CTRL MMIOH End Address register

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PCIe_CTRL_x16_MMIOH2L_TR_START_ADDR, x16 CTRL MMIOH2L Translated Region Start Address register

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PCIe_CTRL_x16_MMIOH2L_TR_END_ADDR, x16 CTRL MMIOH2L Translated Region End Address register

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PCIe_CTRL_x16_CFG_END_ADDR, x16 CTRL Configuration End Address register

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PCIe_CTRL_x16_ECAM2_START_ADDR, x16 CTRL ECAM2 Start Address register

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PCIe_CTRL_x16_ECAM2_END_ADDR, x16 CTRL ECAM2 End Address register

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PCIe_CTRL_x8_ECAM2_ADDR_CTRL, x16 CTRL ECAM2 Address Control register

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PID_4, PCIe Integration Control Peripheral ID 4 register

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PID_0, PCIe Integration Control Peripheral ID 0 register

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PID_1, PCIe Integration Control Peripheral ID 1 register

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PID_2, PCIe Integration Control Peripheral ID 2 register

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PID_3, PCIe Integration Control Peripheral ID 3 register

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COMP_ID0, PCIe Integration Control Component ID 0 register

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COMP_ID1, PCIe Integration Control Component ID 1 register

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COMP_ID2, PCIe Integration Control Component ID 2 register

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COMP_ID3, PCIe Integration Control Component ID 3 register

# metadata.contentDescription
Provides a high-level overview of Arm Neoverse N2 reference design, including the system architecture and the functional description.