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Arm Neoverse Coherent Mesh Network CMN-700  Technical Reference Manual

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Arm® Neoverse™ CMN‑700 Coherent Mesh Network Technical Reference Manual

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I/O coherent Home Node with PCIe optimization

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CML Symmetric Multiprocessor (SMP) support

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Tunneling PCIe traffic through CML SMP link

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Streaming PCIe write traffic through CML SMP link

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Dedicated RN-I resources for AXI port traffic

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Topology considerations when using extra device ports

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DTM changes when using extra device ports 

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RN entry to and exit from Snoop and DVM domains

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Node ID mapping for XP with extra device ports 

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Address range-based QoS override and PrefetchTarget support

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Support for PrefetchTarget operations in RN SAM

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RN SAM Compact HN Tables for multi-chip configurations 

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Local HN-F and CPAG hash index: shuttering from total hash index bits 

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HN‑F to SN-F memory striping in HN‑F SAM

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GIC communication over AXI4-Stream ports

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Rules for avoiding deadlocks in non-XY routing

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PCIe manager and subordinate restrictions and requirements

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Error Detection and Deferred Error values

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Error detection, signaling, and reporting

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Support for early completion of DVMOp requests

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Remote DVM Optimization based on VMID filtering

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Node configuration register address mapping

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Requirements of configuration register reads and writes

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RNSAM programming with power-of-two hashing 

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RNSAM programming for Prefetch Target to a non-hash region

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CMN‑700 SAM programming for Hierarchical Hashing

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Programming sequence to enable CXL.mem regions inside HNSAM

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Multichip flat, 64B interleaving across 4 chips: (tgt_type = HN-Fs)

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HNF interleave across local/remote HNF at cache line interleaving of 64bytes

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HNF interleave across local/remote HNF: 4K interleaving across chips and 64 bytes interleaving across HNFs

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Program the dual DAT and RSP channel selection scheme

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Discover and bring up a local CMN‑700 system

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Program CML system to enable CML_SMP communication

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Options when programming CCG auxiliary control and configuration control registers

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Assign LinkIDs to remote CML protocol links

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Program CML protocol link control registers

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Programming to enable tunneling of PCIe traffic

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Programming to enable PCIe write streaming through CML SMP link

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Establish protocol link up between CML gateway and remote CML link

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Link down protocol link between CML gateway and remote CML link

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Entry and exit protocol links from coherency domains and DVM domains

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Program CML system to enable CXL communication

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Programming optimization for DVMs and CPU events

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SLC memory system components and configuration

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Non-clustered and clustered modes for SF RN‑F tracking

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Configuring non-clustered RN‑F tracking in HN‑F SF

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Configuring clustered mode for SF tracking

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Identifying clusters and individual devices in clustered mode

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Error reporting and software-configured error injection

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Transaction handling in SLC memory system

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CMO and PCMO propagation from HN‑F to SN‑F or SBSX

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Memory System Performance Resource Partitioning and Monitoring

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HN‑F class-based resource allocation and arbitration

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Request retry based on POCQ resource allocation

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Performance Monitoring Unit system overview

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PCIe read Burst preservation through the interconnect

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RN‑I and RN‑D AxID-based target selection

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CMN buffer lifetime and recommended parameter settings

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Requested read bandwidth at RN‑I bridges

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Read bandwidth on interconnect at SBSX bridges

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Total requested bandwidth at SBSX bridges

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Delays at SBSX bridges because of backpressure

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Read bandwidth on interconnect at HN‑I bridges

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Total requested bandwidth at HN‑I bridges

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Delays at HN‑I bridges because of ordering requirements

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Delays at HN‑I bridges because of backpressure

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Occupancy and lifetime measurement using PMU events

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HN‑I and HN‑P AxID signal properties and encodings

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Conditions for tying off AXI/ACE-Lite master interface pins

# metadata.contentDescription
This book is for the Arm Neoverse CMN‑700 Coherent Mesh Network product.