# title
Arm Cortex-R52+ Processor Technical Reference Manual

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Arm® Cortex®-R52+ Processor Technical Reference Manual

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Advanced SIMD and floating-point support

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 Advanced Microcontroller Bus Architecture (AMBA) interfaces

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Advanced Peripheral Bus (APB) Debug interface

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Terminology for returning from an exception

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AArch32 exception and fault handling registers

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Architectural Feature Access Control Register

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Auxiliary Instruction Fault Status Register

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Auxiliary Memory Attribute Indirection Register 0

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Auxiliary Memory Attribute Indirection Register 1

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Data Cache Error Record Registers 0 and 1

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EL0 Read/Write Software Thread ID Register

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EL0 Read-Only Software Thread ID Register

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Hyp Auxiliary Data Fault Status Register

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Hyp Auxiliary Instruction Fault Status Register

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Hyp Auxiliary Memory Attribute Indirection Register 0

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Hyp Auxiliary Memory Attribute Indirection Register 1

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Hyp Memory Attribute Indirection Register 0 and 1

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Hyp Protection Region Base Address Register

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Hyp Protection Region Limit Address Register

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Hyp Protection Region Selection Register

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Instruction Cache Error Record Registers 0 and 1

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Memory Attribute Indirection Registers 0 and 1

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Protection Region Limit Address Register

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Event communication using WFE and SEV instructions

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CLREXMON request and acknowledge signaling

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Interrupt Controller Hyp Control Register

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Interrupt Controller Hyp Control VGIC Type Register

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Interrupt Controller Hyp Maintenance Interrupt Status Register EL2

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Interrupt Controller End of Interrupt Status Register

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Interrupt Controller Empty List Register Status Register

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Interrupt Controller Virtual Machine Control Register

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Interrupt Controller List Registers 0-3, ICH_LR0-3

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Interrupt Controller List Registers 0-3, ICH_LRC0-3

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Interrupt Controller Hyp Active Priorities Group 0 Register 0

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Interrupt Controller Hyp Active Priorities Group 1 Register 0

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Interrupt Controller Interrupt Acknowledge Register 0

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Interrupt Controller Interrupt Acknowledge Register 1

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Interrupt Controller End Of Interrupt Register 0

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Interrupt Controller End Of Interrupt Register 1

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Interrupt Controller Highest Priority Pending Interrupt Register 0

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Interrupt Controller Highest Priority Pending Interrupt Register 1

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Interrupt Controller Binary Point Register 0

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Interrupt Controller Binary Point Register 1

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Interrupt Controller Interrupt Priority Mask Register

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Interrupt Controller Running Priority Register

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Interrupt Controller Control Register (EL1)

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Interrupt Controller System Register Enable Register (EL1)

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Interrupt Controller System Register Enable Register (EL2)

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Interrupt Controller Interrupt Group 0 Enable Register

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Interrupt Controller Interrupt Group 1 Enable Register

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Interrupt Controller Software Generated Interrupt Group 0 Register

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Interrupt Controller Software Generated Interrupt Group 1 Register

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Interrupt Controller Alias Software Generated Interrupt Group 1 Register

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Interrupt Controller Active Priorities Group 0 Register

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Interrupt Controller Active Priorities Group 1 Register

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Interrupt Controller Virtual Interrupt Acknowledge Register 0

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Interrupt Controller Virtual Interrupt Acknowledge Register 1

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Interrupt Controller Virtual End Of Interrupt Register 0

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Interrupt Controller Virtual End Of Interrupt Register 1

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Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0

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Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1

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Interrupt Controller Virtual Binary Point Register 0

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Interrupt Controller Virtual Binary Point Register 1

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Interrupt Controller Deactivate Virtual Interrupt Register

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Interrupt Controller Virtual Interrupt Priority Mask Register

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Interrupt Controller Virtual Running Priority Register

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Interrupt Controller Virtual Control Register

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Interrupt Controller Virtual Interrupt Group 0 Enable Register

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Interrupt Controller Virtual Interrupt Group 1 Enable Register

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Interrupt Controller Virtual Active Priorities Group 0 Register

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Interrupt Controller Virtual Active Priorities Group 1 Register

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External Debug Calibration Control Register

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External Debug Peripheral Identification Register 0

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External Debug Peripheral Identification Register 1

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External Debug Peripheral Identification Register 2

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External Debug Peripheral Identification Register 3

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External Debug Peripheral Identification Register 4

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External Debug Component Identification Register 0

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External Debug Component Identification Register 1

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External Debug Component Identification Register 2

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External Debug Component Identification Register 3

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External Debug AArch32 Processor Feature Register

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External Debug Processor Feature Register 

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ROM table Debug Peripheral Identification Registers

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ROM table Debug Peripheral Identification Register 0

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ROM table Debug Peripheral Identification Register 1

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ROM table Debug Peripheral Identification Register 2

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ROM table Debug Peripheral Identification Register 3

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ROM table Debug Peripheral Identification Register 4

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ROM table Debug Peripheral Identification Register 5-7

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ROM table Debug Component Identification Registers

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ROM table Debug Component Identification Register 0

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ROM table Debug Component Identification Register 1

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ROM table Debug Component Identification Register 2

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ROM table Debug Component Identification Register 3

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Performance Monitors Common Event Identification Register 0

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Performance Monitors Common Event Identification Register 1

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Performance Monitors Peripheral Identification Register 0

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Performance Monitors Peripheral Identification Register 1

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Performance Monitors Peripheral Identification Register 2

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Performance Monitors Peripheral Identification Register 3

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Performance Monitors Peripheral Identification Register 4

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Performance Monitors Peripheral Identification Register 5-7

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Performance Monitors Component Identification Register 0

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Performance Monitors Component Identification Register 1

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Performance Monitors Component Identification Register 2

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Performance Monitors Component Identification Register 3

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ETM trace unit generation options and resources

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ViewData Include/Exclude Single Address Comparator Register

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ViewData Include/Exclude Address Range Comparator Register

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Sequencer State Transition Control Registers, n=0-2

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Single-shot Comparator Control Registers, n=0-1

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Single-shot Comparator Status Registers n=0-1

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Address Comparator Value Registers, n=0-7

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Address Comparator Access Type Registers, n=0-7

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Data Value Comparator Value Registers, n=0-1

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Data Value Comparator Mask Registers, n=0-1

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Virtual Context Identifier Comparator Value Register

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 Context ID Comparator Control Register 0 

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Advanced SIMD and floating-point support

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About the Advanced SIMD and floating-point support

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Accessing the feature identification registers

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Floating-point Status and Control Register

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Media and Floating-point Feature Register 0

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Media and Floating-point Feature Register 1

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Media and Floating-point Feature Register 2

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Memory correcting error reporting signals

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AXIM signal integrity protection signals

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AXIM read address signal integrity protection signals

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AXIM read data signal integrity protection signals

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AXIM write address signal integrity protection signals

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AXIM write data signal integrity protection signals

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AXIM write response signal integrity protection signals

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AXIM read address interconnect protection signal

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AXIM read data interconnect protection signals

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AXIM write address interconnect protection signal

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AXIM write data interconnect protection signals

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AXIM write response interconnect protection signal

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AXIM read data integrity protection signals

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AXIM write data integrity protection signals

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AXIS signal integrity protection signals

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AXIS read address signal integrity protection signals

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AXIS read data signal integrity protection signals

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AXIS write address signal integrity protection signals

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AXIS write data signal integrity protection signals

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AXIS write response signal integrity protection signals

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AXIS read address interconnect protection signal

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AXIS read data interconnect protection signals

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AXIS write address interconnect protection signals

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AXIS write data interconnect protection signals

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AXIS write response interconnect protection signal

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AXIS read data integrity protection signals

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AXIS write data integrity protection signals

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LLPP signal integrity protection signals

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LLPP read address signal integrity protection signals

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LLPP read data signal integrity protection signals

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LLPP write address signal integrity protection signals

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LLPP write data signal integrity protection signals

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LLPP write response signal integrity protection signals

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LLPP read address interconnect protection signals

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LLPP read data interconnect protection signals 

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LLPP write address interconnect protection signal

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LLPP write data interconnect protection signals

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LLPP write response interconnect protection signal

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LLPP read data integrity protection signals

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LLPP write data integrity protection signals

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Flash signal integrity protection signals

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Flash read address signal integrity protection signals

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Flash read data signal integrity protection signals

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Flash read address interconnect protection signals

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Flash read data interconnect protection signals

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Flash read data integrity protection signals

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GIC Distributor external messaging port signals

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About cycle timings and interlock behavior

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Floating-point and Advanced SIMD instructions cycle timings

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UNPREDICTABLE instructions within an IT block

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Specific UNPREDICTABLE cases for instructions 

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STR (Immediate, Thumb), STR (Immediate, Arm), STR (register), STRB (immediate, Thumb), STRB (immediate, Arm), STRB (register), STRBT, STRH (immediate, Thumb), STRH (immediate, Arm), STRH (register), STRHT, and STRT 

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STREX, STREXB, STREXD, STREXH, STLEX, STLEXB, STLEXD, and STLEXH

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Load/Store accesses crossing MPU regions

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Crossing an MPU region with different memory types or shareability attributes

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Crossing a 4KB boundary with Device (or Strongly-Ordered) accesses

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Example of externally integrated PMC-R52+

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Example of a pre-integrated PMC-Cortex-R52+

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Example short-burst software transparent on-line MBIST test algorithm

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PMC-R52+ programming for March C- algorithm

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Integration Mode Control Register, ITCTRL

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Device ID Registers, DEVID, DEVID1, and DEVID2

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Device Type Identifier Register, DEVTYPE

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Peripheral Identification Register 7, PIDR7

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Peripheral Identification Register 6, PIDR6

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Peripheral Identification Register 5, PIDR5

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Peripheral Identification Register 4, PIDR4

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Peripheral Identification Register 3, PIDR3

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Peripheral Identification Register 2, PIDR2

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Peripheral Identification Register 1, PIDR1

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Peripheral Identification Register 0, PIDR0

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Component Identification Register 3, CIDR3

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Component Identification Register 2, CIDR2

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Component Identification Register 1, CIDR1

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Component Identification Register 0, CIDR0

# metadata.contentDescription
This manual is for the Cortex -R52+ processor. It provides reference information and contains programming details for registers. It also describes the memory system, the interrupts, the debug features, and other key features of the processor.