# title
Arm Cortex-M85 Processor Devices Generic User Guide

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Arm® Cortex®-M85 Processor Devices Generic User Guide

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About the Cortex-M85 processor and core peripherals

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The Cortex-M85 Processor, Reference Material

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Processor modes and privilege levels for software execution

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Combined Exception Return Program Status Register, RETPSR

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Exception continuation flags for beat-wise vector instructions

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Vector Predication Status and Control Register, VPR

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Pointer Authentication Key Privileged Register, n = 0 - 3

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Pointer Authentication Key Unprivileged Register, n = 0 - 3

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The Cortex Microcontroller Software Interface Standard

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Secure memory system and memory partitioning

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Additional memory access constraints for caches and shared memory

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Programming hints for the synchronization primitives

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Fault status registers and fault address registers

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The Cortex-M85 Instruction Set, Reference Material

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Binary compatibility with other Cortex processors

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List of CMSIS functions to generate some processor instructions

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CMSIS functions to access the special registers

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CMSIS functions to access the Non-secure special registers

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List of multiply and divide instructions

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SMLAWB, SMLAWT, SMLABB, SMLABT, SMLATB, and SMLATT

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SMLALD, SMLALDX, SMLALBB, SMLALBT, SMLALTB, and SMLALTT

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List of packing and unpacking instructions

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VCVT and VCVTR from floating-point and integer

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VCVT between floating-point and fixed-point

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VMOV half of doubleword to single general-purpose register

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VMOV general-purpose register to half-precision

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VMOV general-purpose register to single-precision register  

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VMOV two general registers to two single-precision registers

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VMOV two general-purpose registers and a double-precision register

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VMOV single general-purpose register to half of doubleword register

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VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ 

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Armv8.1‑M shift, saturate, and reverse operations instructions

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List of Armv8.1‑M shift, saturate, and reverse operations instructions

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List of Armv8.1‑M branch and loop instructions

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Armv8.1‑M comparison and vector predication operations instructions

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List of Armv8.1‑M comparison and vector predication operations instructions

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Armv8.1‑M vector load and store operations instructions

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List of Armv8.1‑M vector load and store operations instructions

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Armv8.1‑M vector move operation instructions

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List of Armv8.1‑M vector move operation instructions

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  VMOV (two 32 bit vector lanes to two general-purpose registers)  

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  VMOV (two general-purpose registers to two 32 bit vector lanes)  

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Armv8.1‑M vector floating-point conversion and rounding operation instructions

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List of Armv8.1‑M vector floating-point conversion and rounding operation instructions

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  VCVT (between floating-point and fixed-point)  

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  VCVT (between floating-point and integer)  

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  VCVT (between single and half-precision floating-point)  

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  VCVT (from floating-point to integer)  

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List of Armv8.1‑M vector arithmetic instructions

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  VFMA (vector by scalar plus vector, floating-point)  

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  VFMAS (vector by vector plus scalar, floating-point)  

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  VMLAS (vector by vector plus scalar)  

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  VQDMLAH, VQRDMLAH (vector by scalar plus vector)  

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  VQDMLASH, VQRDMLASH (vector by vector plus scalar)  

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Armv8.1‑M vector bitwise operations instructions

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List of Armv8.1‑M vector bitwise operations instructions

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  VMOV (general-purpose register to vector lane)  

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  VMOV (vector lane to general-purpose register)  

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Cortex-M85 Processor-level components and system registers , Reference Material

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Accessing the NVIC registers using CMSIS

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Hardware and software control of interrupts

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System Control and Implementation Control Block

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Application Interrupt and Reset Control Register

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System Handler Control and State Register 

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System Control Block design hints and tips

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Implementation control block register summary

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Instruction Cache Invalidate All to PoU, ICIALLU

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Instruction Cache line Invalidate by Address to PoU, ICIMVAU

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Data Cache line Invalidate by Address to PoC, DCIMVAC

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Data Cache line Invalidate by Set/Way, DCISW

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Data cache clean by address to the PoU, DCCMVAU

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Data cache line clean by address to the PoC, DCCMVAC

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Data Cache Clean and Invalidate by Address to the PoC, DCCIMVAC

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Data Cache Clean and Invalidate by Set/Way, DCCISW

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Accessing the NVIC cache maintenance operations using CMSIS

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Initializing the instruction and data cache

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Enabling the instruction and data cache 

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Security Attribution Unit register summary

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Security Attribution Unit Control Register

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Security Attribution Unit Region Number Register

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Security Attribution Unit Region Base Address Register

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Security Attribution Unit Region Limit Address Register

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MPU Region Base Address Register Alias, n=1-3

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MPU Region Limit Address Register Alias, n=1-3

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MPU Memory Attribute Indirection Registers 0 and 1

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Implementation defined memory system control registers

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Direct Cache Access Location Registers, DCAICLR and DCADCLR

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Direct Cache Access Read Registers, DCAICRR and DCADCRR

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TCM Control Registers, ITCMCR and DTCMCR

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ITGU and DTGU Control Registers, ITGU_CTRL and DTGU_CTRL

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ITGU and DTGU Configuration Registers, ITGU_CFG and DTGU_CFG

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ITGU and DTGU Look Up Table Registers, ITGU_LUTn and DTGU_LUTn

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Implementation defined power mode control

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Core Power Domain Low Power State Register, CPDLPSTATE

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Debug Power Domain Low Power State Register, DPDLPSTATE

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Implementation defined error banking registers

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Instruction Cache Error Bank Register 0-1, IEBR0 and IEBR1

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Data Cache Error Bank Register 0-1, DEBR0 and DEBR1

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TCM Error Bank Register 0-1, TEBR0 and TEBR1

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Data for TCU Error Bank Register 0-1, TEBRDATA0 and TEBRDATA1

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Processor configuration information read data register, CFGINFORD

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Floating-point Context Control Register, FPCCR

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Floating-point Context Address Register, FPCAR

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Floating-point Status Control Register, FPSCR

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Floating-point Default Status Control Register

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Cortex-M85 processor implementation of RAS

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Error processing in the L1 data and instruction cache

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Address decoder protection and white noise protection

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ERRFR0, RAS Error Record Feature Register

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ERRSTATUS0, RAS Error Record Primary Status Register

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ERRADDR0 and ERRADDR20, RAS Error Record Address Registers

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ERRMISC10, Error Record Miscellaneous Register 10

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ERRGSR0, RAS Fault Group Status Register

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ERRDEVID, RAS Error Record Device ID Register

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Performance Monitoring Unit Extension support

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Performance Monitoring Unit Event Counter Register, PMU_EVCNTR0-7

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Performance Monitoring Unit Cycle Counter Register, PMU_CCNTR

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Performance Monitoring Unit Event Type and Filter Register, PMU_EVTYPER0-7

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Performance Monitoring Unit Count Enable Set Register, PMU_CNTENSET

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Performance Monitoring Unit Count Enable Clear Register, PMU_CNTENCLR

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Performance Monitoring Unit Interrupt Enable Set Register, PMU_INTENSET

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Performance Monitoring Unit Interrupt Enable Clear Register, PMU_INTENCLR

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Performance Monitoring Unit Overflow Flag Status Clear Register, PMU_OVSCLR

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Performance Monitoring Unit Overflow Flag Status Set Register, PMU_OVSSET

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Performance Monitoring Unit Software Increment Register, PMU_SWINC

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Performance Monitoring Unit Type Register, PMU_TYPE

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Performance Monitoring Unit Control Register, PMU_CTRL

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Performance Monitoring Unit Device Architecture Register, PMU_DEVARCH

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Performance Monitoring Unit Device Type Register, PMU_DEVTYPE

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Performance Monitoring Unit Peripheral Identification Register 0, PMU_PIDR0

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Performance Monitoring Unit Peripheral Identification Register 1, PMU_PIDR1

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Performance Monitoring Unit Peripheral Identification Register 2, PMU_PIDR2

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Performance Monitoring Unit Peripheral Identification Register 3, PMU_PIDR3

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Performance Monitoring Unit Peripheral Identification Register 4, PMU_PIDR4

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Performance Monitoring Unit Component Identification Register 0, PMU_CIDR0

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Performance Monitoring Unit Component Identification Register 1, PMU_CIDR1

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Performance Monitoring Unit Component Identification Register 2, PMU_CIDR2

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Performance Monitoring Unit Component Identification Register 3, PMU_CIDR3

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EWIC Automatic Sequence Control Register

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EWIC Device Type Identifier Register, EWIC_DEVTYPE

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Peripheral Identification Register 4, EWIC_PIDR4

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Peripheral Identification Register 5, EWIC_PIDR5

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Peripheral Identification Register 6, EWIC_PIDR6

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Peripheral Identification Register 7, EWIC_PIDR7

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Peripheral Identification Register 0, EWIC_PIDR0

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Peripheral Identification Register 1, EWIC_PIDR1

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Peripheral Identification Register 2, EWIC_PIDR2

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Peripheral Identification Register 3, EWIC_PIDR3

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Component Identification Register 0, EWIC_ CIDR0

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Component Identification Register 1, EWIC_ CIDR1

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Component Identification Register 2, EWIC_ CIDR2

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Component Identification Register 3, EWIC_ CIDR3

# metadata.contentDescription
This book is a generic user guide for devices that implement the Cortex -M85 processor. Implementers of Cortex -M85 designs make several implementation choices that can affect the functionality of the device. This means that, in this book some information is described as implementation-defined, and some features are described as optional. In this book, unless the context indicates otherwise, processor refers to the Cortex -M85 processor, as supplied by Arm, and device refers to an implemented device, which is supplied by an Arm partner, that incorporates a Cortex -M85 processor. In particular, your device refers to the particular implementation of the Cortex -M85 processor that you are using. Some features of your device depend on the implementation choices made by the Arm partner that made the device.