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Arm CoreSight ETM-M85 Technical Reference Manual

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Arm® CoreSight™ ETM-M85 Technical Reference Manual

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TRCTSCTLR, Global Timestamp Control Register

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TRCVICTLR, ViewInst Main Control Register

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TRCVIPCSSCTLR, ViewInst Start/Stop Processor Comparator Control Register

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TRCEXTINSELR, External Input Select Register

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TRCCNTRLDVR0, Counter Reload Value Register 0

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TRCRSCTLRn, Resource Selection Registers 2-3 

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TRCSSCCR0, Single-shot Comparator Control Register 0

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TRCSSCSR0, Single-shot Comparator Status Register 0

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TRCSSPCICR0, Single-shot Processor Comparator Input Control Register 0

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TRCITIATBINR, Integration Instruction ATB In Register

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TRCITIATBOUTR, Integration Instruction ATB Out Register

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TRCITCTRL, Integration Mode Control Register

# metadata.contentDescription
This book is for the CoreSight Embedded Trace Macrocell for the Cortex -M85 processor. You implement ETM- M85 with the Cortex -M85 processor. In this manual, in general, any reference to the processor applies to the Cortex -M85 processor, as appropriate.