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Arm CoreLink AHB Cache Technical Reference Manual Revision r0p0

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Arm CoreLink AHB Cache Technical Reference Manual

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Latency and stalling on the AHB interface

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Clean and invalidate by address maintenance

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MAINT_CTRL_ALL, maintenance control for the entire cache register

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MAINT_CTRL_LINES, maintenance control for individual lines register

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MAINT_STATUS, maintenance status for the cache register

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SECIRQSTAT, Secure interrupt request status register

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SECIRQSCLR, Secure interrupt status clear register

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SECIRQEN, Secure interrupt enable register

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SECIRQINFO1, Secure transfer error information register 1

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SECIRQINFO2, Secure transfer error information register 2

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NSECIRQSTAT, Non-secure interrupt request status register

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NSECIRQSCLR, Non-secure interrupt status clear register

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NSECIRQEN, Non-secure interrupt enable register

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NSECIRQINFO1, Non-secure transfer error information register 1

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NSECIRQINFO2, Non-secure transfer error information register 2

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SECSTATCTRL, Secure transfers statistic counters control

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NSECHIT, Non-secure transfers hit register

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NSECMISS, Non-secure transfers miss register

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NSECSTATCTRL, Non-secure transfers statistic counters control register

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PMSVR0, saved value register 0 - Secure hit

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PMSVR1, saved value register 1 - Secure miss

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PMSVR2, saved value register 2 - Non-secure hit

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PMSVR3, saved value register 3 - Non-secure miss

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Enable the AHB Cache by using software with automatic maintenance on

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Enable the AHB Cache by using software with automatic maintenance off

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Disable the AHB Cache by using software with automatic maintenance on

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Disable the AHB Cache by using software with automatic maintenance off

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Use Non-secure software to check cache enable status

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Configurable cache diagnostics available for Non-secure software

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Use software for manual maintenance on the AHB Cache

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Use Secure software to perform manual clean all or invalidate all maintenance

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Use Secure software to perform manual maintenance by address

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Use Non-secure software to perform manual maintenance by address

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Use software to access the statistics counters in the AHB Cache

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Use Secure software to access the Non-secure statistics counters

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Use Non-secure software to access the Non-secure statistics counters

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Sleep mode with cache RAMs in power down state

# metadata.contentDescription
Describes the functionality of the components in the Arm CoreLink AHB Cache. It also provides the programming information and the signal descriptions.