# title
Arm Cortex‑A78AE Core Technical Reference Manual

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Arm® Cortex®‑A78AE Core Technical Reference Manual

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Clocks, resets, and input synchronization

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About clocks, resets, and input synchronization

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Specific behaviors on aborts and memory attributes

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Instruction cache speculative memory accesses

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Encoding for L1 instruction cache tag, L1 instruction cache data, L1 BTB, L1 GHB, L1 BIM, L1 TLB instruction, and L0 macro-op cache data

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Encoding for L1 data cache tag, L1 data cache data, and L1 TLB data

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Generic Interrupt Controller CPU interface

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About the Generic Interrupt Controller CPU interface

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Advanced SIMD and floating-point support

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About the Advanced SIMD and floating-point support

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Accessing the feature identification registers

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AArch32 architectural system register summary

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AArch64 architectural system register summary

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AArch64 implementation defined register summary

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ACTLR_EL1, Auxiliary Control Register, EL1

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ACTLR_EL2, Auxiliary Control Register, EL2

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ACTLR_EL3, Auxiliary Control Register, EL3

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AFSR0_EL1, Auxiliary Fault Status Register 0, EL1

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AFSR0_EL2, Auxiliary Fault Status Register 0, EL2

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AFSR0_EL3, Auxiliary Fault Status Register 0, EL3

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AFSR1_EL1, Auxiliary Fault Status Register 1, EL1

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AFSR1_EL2, Auxiliary Fault Status Register 1, EL2

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AFSR1_EL3, Auxiliary Fault Status Register 1, EL3

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AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1

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AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2

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AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3

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APDAKeyHi_EL1, Pointer Authentication Key A for Data

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APDAKeyLo_EL1, Pointer Authentication Key A for Data

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APDBKeyHi_EL1, Pointer Authentication Key B for Data

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APDBKeyLo_EL1, Pointer Authentication Key B for Data

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APGAKeyHi_EL1, Pointer Authentication Key A for Code

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APGAKeyLo_EL1, Pointer Authentication Key A for Code

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APIAKeyHi_EL1, Pointer Authentication Key A for Instruction

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APIAKeyLo_EL1, Pointer Authentication Key A for Instruction

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APIBKeyHi_EL1, Pointer Authentication Key B for Instruction

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APIBKeyLo_EL1, Pointer Authentication Key B for Instruction

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ATCR_EL1, Auxiliary Translation Control Register, EL1

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ATCR_EL2, Auxiliary Translation Control Register, EL2

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ATCR_EL12 , Alias to Auxiliary Translation Control Register EL1

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ATCR_EL3, Auxiliary Translation Control Register, EL3

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AVTCR_EL2, Auxiliary Virtualized Translation Control Register, EL2

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CLIDR_EL1, Cache Level ID Register, EL1 

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CPACR_EL1, Architectural Feature Access Control Register, EL1

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CPTR_EL2, Architectural Feature Trap Register, EL2

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CPTR_EL3, Architectural Feature Trap Register, EL3

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CPUACTLR_EL1, CPU Auxiliary Control Register, EL1

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CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1

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CPUACTLR3_EL1, CPU Auxiliary Control Register 3, EL1

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CPUACTLR5_EL1, CPU Auxiliary Control Register 5, EL1

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CPUACTLR6_EL1, CPU Auxiliary Control Register 6, EL1

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CPUCLLCTLR_EL1, Cache Line Lockout Control Register, EL1

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CPUCLL0_EL1, CPU Cache Line Lockout Register, EL1

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CPUCLL1_EL1, CPU Cache Line Lockout Register, EL1

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CPUCFR_EL1, CPU Configuration Register, EL1

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CPUECTLR_EL1, CPU Extended Control Register, EL1 

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CPUECTLR2_EL1, CPU Extended Control Register2, EL1 

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CPUPCR_EL3, CPU Private Control Register, EL3

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CPUPFR_EL3, CPU Private Flag Register, EL3

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CPUPMR_EL3, CPU Private Mask Register, EL3

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CPUPMR2_EL3, CPU Private Mask Register 2, EL3

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CPUPOR_EL3, CPU Private Operation Register, EL3

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CPUPOR2_EL3, CPU Private Operation Register 2, EL3

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CPUPPMCR_EL3, CPU Power Performance Management Configuration Register, EL3

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CPUPSELR_EL3, CPU Private Selection Register, EL3

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CPUPWRCTLR_EL1, Power Control Register, EL1

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CSSELR_EL1, Cache Size Selection Register, EL1

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DCZID_EL0, Data Cache Zero ID Register, EL0

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DISR_EL1, Deferred Interrupt Status Register, EL1

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ERRSELR_EL1, Error Record Select Register, EL1 

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ERXADDR_EL1, Selected Error Record Address Register, EL1

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ERXCTLR_EL1, Selected Error Record Control Register, EL1

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ERXFR_EL1, Selected Error Record Feature Register, EL1

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ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1

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ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1

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ERXPFGCDN_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1

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ERXPFGCTL_EL1, Selected Error Pseudo Fault Generation Control Register, EL1

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ERXPFGF_EL1, Selected Pseudo Fault Generation Feature Register, EL1

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ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1

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ESR_EL1, Exception Syndrome Register, EL1

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ESR_EL2, Exception Syndrome Register, EL2

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ESR_EL3, Exception Syndrome Register, EL3

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HACR_EL2, Hyp Auxiliary Configuration Register, EL2

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HCR_EL2, Hypervisor Configuration Register, EL2

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ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0

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ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1

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ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1

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ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1

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ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1

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ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1

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ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1

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ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1

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ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1

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ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1

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ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1

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ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1

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ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1

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ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1

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ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1

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ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1

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ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1

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ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1

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ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1

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ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1

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ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1

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ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1

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ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1

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ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1

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ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1

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ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1

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ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1

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ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1

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LORC_EL1, LORegion Control Register, EL1

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MDCR_EL3, Monitor Debug Configuration Register, EL3

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MPIDR_EL1, Multiprocessor Affinity Register, EL1

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RVBAR_EL3, Reset Vector Base Address Register, EL3

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TCR_EL1, Translation Control Register, EL1

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TCR_EL2, Translation Control Register, EL2

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TCR_EL3, Translation Control Register, EL3

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TTBR0_EL1, Translation Table Base Register 0, EL1

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TTBR0_EL2, Translation Table Base Register 0, EL2

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TTBR0_EL3, Translation Table Base Register 0, EL3 

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TTBR1_EL1, Translation Table Base Register 1, EL1

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TTBR1_EL2, Translation Table Base Register 1, EL2

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VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2

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VSESR_EL2, Virtual SError Exception Syndrome Register

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VTCR_EL2, Virtualization Translation Control Register, EL2

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VTTBR_EL2, Virtualization Translation Table Base Register, EL2

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ERR0MISC0, Error Record Miscellaneous Register 0

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ERR0MISC1, Error Record Miscellaneous Register 1

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ERR0PFGCDN, Error Pseudo Fault Generation Count Down Register

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ERR0PFGCTL, Error Pseudo Fault Generation Control Register

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ERR0PFGF, Error Pseudo Fault Generation Feature Register

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ERR0STATUS, Error Record Primary Status Register

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AArch64 physical GIC CPU interface system register summary

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ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1

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ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Register 0 EL1

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ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0, EL1

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ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1, EL1

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ICC_CTLR_EL1, Interrupt Controller Control Register, EL1

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ICC_CTLR_EL3, Interrupt Controller Control Register, EL3

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ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1

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ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2

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ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3

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AArch64 virtual GIC CPU interface register summary

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ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Register 0, EL1

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ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities Group 1 Register 0, EL1

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ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0, EL1

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ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1

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ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1

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AArch64 virtual interface control system register summary

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ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Group 0 Register 0, EL2

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ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Group 1 Register 0, EL2

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ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2

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ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2

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ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2

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Advanced SIMD and floating-point registers

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MVFR0_EL1, Media and VFP Feature Register 0, EL1

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MVFR1_EL1, Media and VFP Feature Register 1, EL1

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MVFR2_EL1, Media and VFP Feature Register 2, EL1

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FPSCR, Floating-Point Status and Control Register

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External access permissions to debug registers

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ETM trace unit generation options and resources

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Programming and reading ETM trace unit registers

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About the statistical profiling extension

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DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1

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DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1

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DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1

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EDCIDR0, External Debug Component Identification Register 0

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EDCIDR1, External Debug Component Identification Register 1

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EDCIDR2, External Debug Component Identification Register 2

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EDCIDR3, External Debug Component Identification Register 3

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EDDEVID, External Debug Device ID Register 0

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EDDEVID1, External Debug Device ID Register 1

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EDPIDR0, External Debug Peripheral Identification Register 0

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EDPIDR1, External Debug Peripheral Identification Register 1

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EDPIDR2, External Debug Peripheral Identification Register 2

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EDPIDR3, External Debug Peripheral Identification Register 3

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EDPIDR4, External Debug Peripheral Identification Register 4

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EDPIDRn, External Debug Peripheral Identification Registers 5-7

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EDRCR, External Debug Reserve Control Register

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PMCEID0, Performance Monitors Common Event Identification Register 0

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PMCEID1, Performance Monitors Common Event Identification Register 1

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PMCEID2, Performance Monitors Common Event Identification Register 2

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PMCR, Performance Monitors Control Register

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PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0

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PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0

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PMCR_EL0, Performance Monitors Control Register, EL0

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CPUPMMIR_EL1, Performance Monitors Machine Identification Register, EL1

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PMCIDR0, Performance Monitors Component Identification Register 0

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PMCIDR1, Performance Monitors Component Identification Register 1

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PMCIDR2, Performance Monitors Component Identification Register 2

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PMCIDR3, Performance Monitors Component Identification Register 3

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PMMIR, Performance Monitors Machine Identification Register

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PMPIDR0, Performance Monitors Peripheral Identification Register 0

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PMPIDR1, Performance Monitors Peripheral Identification Register 1

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PMPIDR2, Performance Monitors Peripheral Identification Register 2

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PMPIDR3, Performance Monitors Peripheral Identification Register 3

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PMPIDR4, Performance Monitors Peripheral Identification Register 4

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PMPIDRn, Performance Monitors Peripheral Identification Register 5-7

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PMPCSSR, PMU Snapshot Program Counter Sample Register

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PMCIDSSR, PMU Snapshot CONTEXTIDR_EL1 Sample Register

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PMCID2SSR, PMU Snapshot CONTEXTIDR_EL2 Sample Register

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PMOVSSR, PMU Snapshot Overflow Status Register

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PMCCNTSR, PMU Snapshot Cycle Counter Register

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PMEVCNTSRn, PMU Event Counter Snapshot Cycle Registers 0-5

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AMCFGR_EL0, Activity Monitors Configuration Register, EL0

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AMCGCR_EL0, Activity Monitors Counter Group Configuration Register, EL0

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AMCNTENCLR0_EL0, Activity Monitors Count Enable Clear Register 0, EL0

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AMCNTENCLR1_EL0, Activity Monitors Count Enable Clear Register 1, EL0

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AMCNTENSET0_EL0, Activity Monitors Count Enable Set Register 0, EL0

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AMCNTENSET1_EL0, Activity Monitors Count Enable Set Register 1, EL0

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AMCR_EL0, Activity Monitors Control Register, EL0

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AMEVCNTR0n_EL0, Activity Monitors Event Counter Registers 0n, EL0

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AMEVCNTR1n_EL0, Activity Monitors Event Counter Registers 1n, EL0

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AMEVTYPER0n_EL0, Activity Monitors Event Type Registers 0n, EL0

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AMEVTYPER1n_EL0, Activity Monitors Event Type Registers 1n, EL0

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AMUSERENR_EL0, Activity Monitors User Enable Register, EL0

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AMCIDR0, Activity Monitors Component Identification Register 0

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AMCIDR1, Activity Monitors Component Identification Register 1

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AMCIDR2, Activity Monitors Component Identification Register 2

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AMCIDR3, Activity Monitors Component Identification Register 3

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AMDEVAFF0, Activity Monitors Device Affinity Register 0

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AMDEVAFF1, Activity Monitors Device Affinity Register 1

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AMDEVARCH, Activity Monitors Device Architecture Register

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AMDEVTYPE, Activity Monitors Device Type Register

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AMPIDR0, Activity Monitors Peripheral Identification Register 0

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AMPIDR1, Activity Monitors Peripheral Identification Register 1

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AMPIDR2, Activity Monitors Peripheral Identification Register 2

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AMPIDR3, Activity Monitors Peripheral Identification Register 3

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AMPIDR4, Activity Monitors Peripheral Identification Register 4

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TRCACATRn, Address Comparator Access Type Registers 0-7

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TRCACVRn, Address Comparator Value Registers 0-7

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TRCBBCTLR, Branch Broadcast Control Register

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TRCCIDCCTLR0, Context ID Comparator Control Register 0

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TRCCIDCVR0, Context ID Comparator Value Register 0

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TRCCIDR0, ETM Component Identification Register 0

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TRCCIDR1, ETM Component Identification Register 1

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TRCCIDR2, ETM Component Identification Register 2

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TRCCIDR3, ETM Component Identification Register 3

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TRCCNTRLDVRn, Counter Reload Value Registers 0-1

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TRCEXTINSELR, External Input Select Register

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TRCIMSPEC0, Implementation Specific Register 0

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TRCITATBCTR0, Trace Integration Test ATB Control Register 0

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TRCITATBCTR1, Trace Integration Test ATB Control Register 1

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TRCITATBCTR2, Trace Integration Test ATB Control Register 2

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TRCITATBDATA0, Trace Integration Test ATB Data Register 0

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TRCITCTRL, Trace Integration Mode Control register

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TRCITMISCIN, Trace Integration Miscellaneous Input Register

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TRCPIDR0, ETM Peripheral Identification Register 0

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TRCPIDR1, ETM Peripheral Identification Register 1

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TRCPIDR2, ETM Peripheral Identification Register 2

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TRCPIDR3, ETM Peripheral Identification Register 3

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TRCPIDR4, ETM Peripheral Identification Register 4

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TRCPIDRn, ETM Peripheral Identification Registers 5-7

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TRCRSCTLRn, Resource Selection Control Registers 2-15

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TRCSEQEVRn, Sequencer State Transition Control Registers 0-2

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TRCSEQRSTEVR, Sequencer Reset Control Register

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TRCSSCCR0, Single-Shot Comparator Control Register 0

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TRCSSCSR0, Single-Shot Comparator Status Register 0

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TRCTSCTLR, Global Timestamp Control Register

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TRCVICTLR, ViewInst Main Control Register

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TRCVMIDCVR0, VMID Comparator Value Register 0

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TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0 

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Load/Store accesses crossing page boundaries

# metadata.contentDescription
This Technical Reference Manual is for the Cortex ‑A78AE core. It provides reference documentation and contains programming details for registers. It also describes the memory system, the caches, the interrupts, and the debug features.