# title
Arm Cortex‑A715 Core Technical Reference Manual

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Arm® Cortex®‑A715 Core Technical Reference Manual

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Cortex‑A715  core powerup and powerdown sequence

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Managing RAS fault and error interrupts during the core powerdown 

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Hardware management of the Access flag and dirty state

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Memory behavior and supported memory types 

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L1 instruction cache Speculative memory accesses

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Instruction implementation in the L1 data memory system

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Error reporting and performance monitoring

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Advanced SIMD and floating-point support

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External access permissions to Debug registers

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Program and read the trace unit registers

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Interaction with the Performance Monitoring Unit and Debug

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Program and read the trace buffer registers

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Statistical Profiling Extension events packet

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Statistical Profiling Extension data source packet

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AArch64 Generic System Control registers summary

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ACTLR_EL1, Auxiliary Control Register (EL1)

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ACTLR_EL2, Auxiliary Control Register (EL2)

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HACR_EL2, Hypervisor Auxiliary Control Register

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ACTLR_EL3, Auxiliary Control Register (EL3)

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AMAIR_EL2, Auxiliary Memory Attribute Indirection Register (EL2)

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AMAIR_EL1, Auxiliary Memory Attribute Indirection Register (EL1)

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AMAIR_EL3, Auxiliary Memory Attribute Indirection Register (EL3)

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IMP_CPUACTLR_EL1, CPU Auxiliary Control Register

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IMP_CPUECTLR_EL1, CPU Extended Control Register

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IMP_CPUECTLR2_EL1, CPU Extended Control Register

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IMP_CPUPWRCTLR_EL1, CPU Power Control Register

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IMP_ATCR_EL2, CPU Auxiliary Translation Control Register

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IMP_AVTCR_EL2, CPU Auxiliary Virtualization Translation Control Register

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IMP_ATCR_EL1, CPU Auxiliary Translation Control Register

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IMP_ISIDE_DATA0_EL3, RAMINDEX Instruction Data register 0

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IMP_ISIDE_DATA1_EL3, RAMINDEX Instruction Data register 1

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IMP_ISIDE_DATA2_EL3, RAMINDEX Instruction Data register 2

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IMP_MMU_DATA0_EL3, RAMINDEX TLB Data register 0

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IMP_MMU_DATA1_EL3, RAMINDEX TLB Data register 1

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IMP_MMU_DATA2_EL3, RAMINDEX TLB Data register 2

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IMP_DSIDE_DATA0_EL3, RAMINDEX L1D Data register 0

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IMP_DSIDE_DATA1_EL3, RAMINDEX L1D Data register 1

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IMP_DSIDE_DATA2_EL3, RAMINDEX L1D Data register 2

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IMP_L2_DATA0_EL3, RAMINDEX L2 Data register 0

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IMP_L2_DATA2_EL3, RAMINDEX L2 Data register 2

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IMP_L2_DATA1_EL3, RAMINDEX L2 Data register 1

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IMP_ATCR_EL3, CPU Auxiliary Translation Control Register

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IMP_CPUPOR_EL3, Selected Instruction Patch Opcode Register

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IMP_CPUPMR_EL3, Selected Instruction Patch Mask Register

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IMP_CPUPOR2_EL3, Selected Instruction Patch Opcode Register 2

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IMP_CPUPMR2_EL3, Selected Instruction Private Mask Register 2

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IMP_CPUPFR_EL3, Selected Instruction Private Flag Register

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AFSR0_EL2, Auxiliary Fault Status Register 0 (EL2)

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AFSR1_EL2, Auxiliary Fault Status Register 1 (EL2)

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AFSR0_EL1, Auxiliary Fault Status Register 0 (EL1)

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AFSR1_EL1, Auxiliary Fault Status Register 1 (EL1)

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AFSR0_EL3, Auxiliary Fault Status Register 0 (EL3)

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AFSR1_EL3, Auxiliary Fault Status Register 1 (EL3)

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AArch64 System instruction registers summary

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MVFR0_EL1, AArch32 Media and VFP Feature Register 0

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MVFR1_EL1, AArch32 Media and VFP Feature Register 1

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MVFR2_EL1, AArch32 Media and VFP Feature Register 2

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ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0

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ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1

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ID_AA64ZFR0_EL1, SVE Feature ID register 0

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ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0

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ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1

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ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0

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ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1

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ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0

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ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1

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ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0

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ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1

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ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2

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CCSIDR_EL1, Current Cache Size ID Register

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GMID_EL1, Multiple tag transfer ID register

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CSSELR_EL1, Cache Size Selection Register

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AArch64 Performance Monitors registers summary

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PMCR_EL0, Performance Monitors Control Register

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PMCEID0_EL0, Performance Monitors Common Event Identification register 0

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PMCEID1_EL0, Performance Monitors Common Event Identification register 1

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ICC_CTLR_EL1, Interrupt Controller Control Register (EL1)

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ICV_CTLR_EL1, Interrupt Controller Virtual Control Register

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ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Registers

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ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Registers

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ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Registers

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ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities Group 1 Registers

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ICH_VTR_EL2, Interrupt Controller VGIC Type Register

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ICC_CTLR_EL3, Interrupt Controller Control Register (EL3)

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AArch64 Other system control registers summary

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ERRSELR_EL1, Error Record Select Register

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ERXFR_EL1, Selected Error Record Feature Register

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ERXCTLR_EL1, Selected Error Record Control Register

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ERXSTATUS_EL1, Selected Error Record Primary Status Register

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ERXADDR_EL1, Selected Error Record Address Register

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ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0

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ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1

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ERXMISC2_EL1, Selected Error Record Miscellaneous Register 2

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ERXMISC3_EL1, Selected Error Record Miscellaneous Register 3

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AArch64 Activity Monitors registers summary

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AMEVTYPER10_EL0, Activity Monitors Event Type Registers 1

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AMEVTYPER11_EL0, Activity Monitors Event Type Registers 1

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AMEVTYPER12_EL0, Activity Monitors Event Type Registers 1

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AMCGCR_EL0, Activity Monitors Counter Group Configuration Register

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AMEVTYPER00_EL0, Activity Monitors Event Type Registers 0

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AMEVTYPER01_EL0, Activity Monitors Event Type Registers 0

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AMEVTYPER02_EL0, Activity Monitors Event Type Registers 0

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AMEVTYPER03_EL0, Activity Monitors Event Type Registers 0

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AArch64 Memory Partitioning and Monitoring registers summary

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MPAMVPMV_EL2, MPAM Virtual Partition Mapping Valid Register

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MPAMVPM0_EL2, MPAM Virtual PARTID Mapping Register 0

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MPAMVPM1_EL2, MPAM Virtual PARTID Mapping Register 1

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CPUPPMCR, Global PPM Configuration Register

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CPUMPMMCR, Global MPMM Configuration Register

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PMPCSSR, Snapshot Program Counter Sample Register

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PMCCNTSR, PMU Cycle Counter Snapshot Register

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PMEVCNTSR0, PMU Event Counter Snapshot Register

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PMEVCNTSR1, PMU Event Counter Snapshot Register

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PMEVCNTSR2, PMU Event Counter Snapshot Register

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PMEVCNTSR3, PMU Event Counter Snapshot Register

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PMEVCNTSR4, PMU Event Counter Snapshot Register

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PMEVCNTSR5, PMU Event Counter Snapshot Register

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PMEVCNTSR6, PMU Event Counter Snapshot Register

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PMEVCNTSR7, PMU Event Counter Snapshot Register

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PMEVCNTSR8, PMU Event Counter Snapshot Register

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PMEVCNTSR9, PMU Event Counter Snapshot Register

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PMEVCNTSR10, PMU Event Counter Snapshot Register

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PMEVCNTSR11, PMU Event Counter Snapshot Register

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PMEVCNTSR12, PMU Event Counter Snapshot Register

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PMEVCNTSR13, PMU Event Counter Snapshot Register

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PMEVCNTSR14, PMU Event Counter Snapshot Register

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PMEVCNTSR15, PMU Event Counter Snapshot Register

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PMEVCNTSR16, PMU Event Counter Snapshot Register

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PMEVCNTSR17, PMU Event Counter Snapshot Register

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PMEVCNTSR18, PMU Event Counter Snapshot Register

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PMEVCNTSR19, PMU Event Counter Snapshot Register

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PMCR_EL0, Performance Monitors Control Register

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PMCEID0, Performance Monitors Common Event Identification register 0

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PMCEID1, Performance Monitors Common Event Identification register 1

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PMCEID2, Performance Monitors Common Event Identification register 2

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PMCEID3, Performance Monitors Common Event Identification register 3

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PMMIR, Performance Monitors Machine Identification Register

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PMDEVARCH, Performance Monitors Device Architecture register

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PMDEVID, Performance Monitors Device ID register

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PMDEVTYPE, Performance Monitors Device Type register

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PMPIDR4, Performance Monitors Peripheral Identification Register 4

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PMPIDR0, Performance Monitors Peripheral Identification Register 0

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PMPIDR1, Performance Monitors Peripheral Identification Register 1

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PMPIDR2, Performance Monitors Peripheral Identification Register 2

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PMPIDR3, Performance Monitors Peripheral Identification Register 3

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PMCIDR0, Performance Monitors Component Identification Register 0

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PMCIDR1, Performance Monitors Component Identification Register 1

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PMCIDR2, Performance Monitors Component Identification Register 2

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PMCIDR3, Performance Monitors Component Identification Register 3

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EDRCR, External Debug Reserve Control Register

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EDACR, External Debug Auxiliary Control Register

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EDPRCR, External Debug Power/Reset Control Register

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EDPFR, External Debug Processor Feature Register

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EDDEVARCH, External Debug Device Architecture register

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EDDEVID2, External Debug Device ID register 2

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EDDEVID1, External Debug Device ID register 1

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EDDEVID, External Debug Device ID register 0

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EDDEVTYPE, External Debug Device Type register

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EDPIDR4, External Debug Peripheral Identification Register 4

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EDPIDR0, External Debug Peripheral Identification Register 0

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EDPIDR1, External Debug Peripheral Identification Register 1

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EDPIDR2, External Debug Peripheral Identification Register 2

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EDPIDR3, External Debug Peripheral Identification Register 3

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EDCIDR0, External Debug Component Identification Register 0

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EDCIDR1, External Debug Component Identification Register 1

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EDCIDR2, External Debug Component Identification Register 2

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EDCIDR3, External Debug Component Identification Register 3

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AMEVTYPER00, Activity Monitors Event Type Registers 0

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AMEVTYPER01, Activity Monitors Event Type Registers 0

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AMEVTYPER02, Activity Monitors Event Type Registers 0

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AMEVTYPER03, Activity Monitors Event Type Registers 0

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AMEVTYPER10, Activity Monitors Event Type Registers 1

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AMEVTYPER11, Activity Monitors Event Type Registers 1

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AMEVTYPER12, Activity Monitors Event Type Registers 1

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AMCGCR, Activity Monitors Counter Group Configuration Register

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AMCFGR, Activity Monitors Configuration Register

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AMDEVARCH, Activity Monitors Device Architecture Register

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AMDEVTYPE, Activity Monitors Device Type Register

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AMPIDR4, Activity Monitors Peripheral Identification Register 4

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AMPIDR0, Activity Monitors Peripheral Identification Register 0

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AMPIDR1, Activity Monitors Peripheral Identification Register 1

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AMPIDR2, Activity Monitors Peripheral Identification Register 2

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AMPIDR3, Activity Monitors Peripheral Identification Register 3

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AMCIDR0, Activity Monitors Component Identification Register 0

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AMCIDR1, Activity Monitors Component Identification Register 1

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AMCIDR2, Activity Monitors Component Identification Register 2

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AMCIDR3, Activity Monitors Component Identification Register 3

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TRCITCTRL, Integration Mode Control Register

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TRCDEVID2, Device Configuration Register 2

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TRCDEVID1, Device Configuration Register 1

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TRCPIDR4, Peripheral Identification Register 4

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TRCPIDR5, Peripheral Identification Register 5

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TRCPIDR6, Peripheral Identification Register 6

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TRCPIDR7, Peripheral Identification Register 7

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TRCPIDR0, Peripheral Identification Register 0

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TRCPIDR1, Peripheral Identification Register 1

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TRCPIDR2, Peripheral Identification Register 2

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TRCPIDR3, Peripheral Identification Register 3

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TRCCIDR0, Component Identification Register 0

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TRCCIDR1, Component Identification Register 1

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TRCCIDR2, Component Identification Register 2

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TRCCIDR3, Component Identification Register 3

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PIDR4, Peripheral Identification Register 4

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PIDR0, Peripheral Identification Register 0

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PIDR1, Peripheral Identification Register 1

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PIDR2, Peripheral Identification Register 2

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PIDR3, Peripheral Identification Register 3

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CIDR0, Component Identification Register 0

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CIDR1, Component Identification Register 1

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CIDR2, Component Identification Register 2

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CIDR3, Component Identification Register 3

# metadata.contentDescription
This manual is for the Cortex ‑A715 core . It provides reference information and contains programming details for registers. It also describes the memory system, the interrupts, the debug features, and other key features of the core .