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Arm CoreLink CI-700 Coherent Interconnect Technical Reference Manual

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Arm® CoreLink™ CI-700 Coherent Interconnect Technical Reference Manual

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I/O coherent Request Node (RN-I) and I/O coherent Request Node with DVM support (RN-D)

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Permitted numbers of devices and system resources in the mesh

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Topology considerations when using extra device ports

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HN-F RAM Power Control State Machine interface

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RN entry to and exit from snoop and DVM domains

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Node ID mapping for configurations with extra device ports

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Support for HN-Fs with CAL in the RN SAM

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Support for PrefetchTgt operations in the RN SAM

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HN-F to SN-F memory striping in HN-F SAM

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Examples of 3-SN and 6-SN mode configurations

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Maintaining contiguous address spaces in SN-Fs

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Configuring HN-I SAM address regions and order regions

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Rules for avoiding deadlocks in non-XY routing

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PCIe master and slave restrictions and requirements

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Generic Interrupt Controller (GIC) communication over AXI4-Stream ports

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Error detection and deferred error values

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Error detection, signaling, and reporting

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Software-configurable error injection in MTSX

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Node configuration register address mapping

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Requirements of configuration register reads and writes

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Programming MTU tag address generation registers

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SLC memory system components and configuration

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Error reporting and software-configured error injection

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Transaction handling in SLC memory system

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CMO and PCMO propagation from HN-F to SN-F or SBSX

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Memory System Performance Resource Partitioning and Monitoring

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QoS class and POCQ resource availability

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DTM changes when using extra device ports

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HN-F MPAM Hard Limit and Soft Limit events

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Requested read bandwidth at RN-I bridges

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Read bandwidth on interconnect at SBSX bridges

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Total requested bandwidth at SBSX bridges

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Delays at SBSX bridges due to backpressure

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Read bandwidth on interconnect at HN-I bridges

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Total requested bandwidth at HN-I bridges

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Delays at HN-I bridges because of ordering requirements

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Delays at HN-I bridges because of backpressure

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Occupancy and lifetime measurement using PMU events

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SBSX and MTSX AxID signal width and field assignments

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Special considerations for AxUSER signals

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Conditions for tying off AXI/ACE-Lite master interface pins

# metadata.contentDescription
This book is for the Arm CoreLink CI-700 Coherent Interconnect product.