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Arm PMC-100 Programmable MBIST Controller Technical Reference Manual

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Arm® PMC-100 Programmable MBIST Controller Technical Reference Manual

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The Arm  PMC-100 Programmable MBIST Controller

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Test memory with on-line MBIST on-line memory use case

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Test memory with on-line MBIST off-line memory use case

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 Standard register initialization and programming

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Data mask, fault bitmap, and data registers, PMC100_DM0-PMC100_DM7

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Loop start program register, PMC100_LSPR

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Loop suspend counter register, PMC100_LSCR

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Test continue counter register, PMC100_TCCR

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Integration Mode Control register, PMC100_ITCTRL

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Claim Tag Clear register, PMC100_CLAIMCLR

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Device Affinity register 0, PMC100_DEVAFF0

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Device Affinity register 1, PMC100_DEVAFF1

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Device Configuration Register 1, PMC100_DEVID1

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Production test March algorithm overview

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On-line MBIST Memory Protection Logic Test Algorithms

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Address Protection Logic Latent Fault Detection algorithm

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Address Protection Logic Single-point Detection algorithm

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Data Protection Logic Latent Fault Detection algorithm

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Data Protection Logic Single-point Fault Detection algorithm

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ECC/parity code field initialization algorithm

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PMC-100 software library configuration and usage

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Release directory structure and file overview

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PMC-100 software library source code file structure

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PMC-100 software library data structures

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Example <core>_pmc100_mem_description<unique>.h file

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PMC-100 software library function parameters

# metadata.contentDescription
This manual is for the PMC-100 . This document describes the behavior of the PMC-100 , including the programmer's model and signals.