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Arm CoreLink MMU-600AE System Memory Management Unit Technical Reference Manual

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Arm® CoreLink™ MMU-600AE System Memory Management Unit Technical Reference Manual

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TBU direct indexing and MTLB partitioning

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AXI USER bits defined by the MMU-600AE TBU

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TCU Queue and Table Walk/Distributed Virtual Memory interface

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DTI interconnect register slice interfaces

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SMMUv3 PMU register architectural options

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Conversion between ACE-Lite and Armv8 attributes

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Completer interface memory type attribute handling

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Requester interface memory type attribute handling

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Transactions that can result in a translation fault

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Transactions that cannot result in a translation fault

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TCU and TBU PMU identification registers

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TCU PMU component and peripheral ID registers

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TBU PMU component and peripheral ID registers

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TCU component and peripheral ID registers

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TCU_QOS, TCU Quality of Service register

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TCU_CFG, TCU Configuration Information register

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TCU_STATUS, TCU Status Information register

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TCU_NODE_CTRLn, TCU Node Control registers

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TCU_NODE_STATUSn, TCU Node Status registers

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TCU_ERRSTATUS, TCU Error Record Primary Syndrome register

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TCU_ERRGEN, TCU Error Generation register

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TBU component and peripheral ID registers

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TBU_ERRSTATUS, TBU Error Record Primary Syndrome register

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TBU_ERRGEN, TBU Error Generation register

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Accessing FMU Error Records using the FMU APB

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Enabling and disabling a Safety Mechanism

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Injecting an error into a Safety Mechanism

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Fault Detection and Control Programmer's View

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FMU_ERR<n>FR, Error Record Feature Register 

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FMU_ERR<n>CTLR, Error Record Control Register 

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FMU_ERR<n>STATUS, Error Record Primary Status Register

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FMU_SMEN, Safety Mechanism Enable Register

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FMU_SMINJERR, Safety Mechanism Inject Error Register

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Integrating the TCU, TBU, LPD, PCIe ATS, and DTI AXI4-Stream interconnect

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TCU QTW/DVM interface signals for MMU-600AE

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TCU programming interface signals for MMU-600AE

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TCU SYSCO interface signals for MMU-600AE

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TCU PMU snapshot interface signals for MMU-600AE

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TCU LPI_PD interface signals for MMU-600AE

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TCU LPI_CG interface signals for MMU-600AE

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TCU APB FMU interface signals for MMU-600AE

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TCU event interface signal for MMU-600AE

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TCU and TBU test and debug signals for MMU-600AE

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TBU PMU snapshot interface signals for MMU-600AE

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TBU LPI_PD interface signals for MMU-600AE

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TBU LPI_CG interface signals for MMU-600AE

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DTI interconnect switch DN_Sn interface signals

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DTI interconnect switch UP_Sn interface signals 

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DTI interconnect switch DN_M interface signals 

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DTI interconnect switch UP_M interface signals 

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DTI interconnect sizer LPI_CG interface signals

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DTI interconnect sizer DN_S interface signals

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DTI interconnect sizer UP_S interface signals

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DTI interconnect sizer DN_M interface signals

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DTI interconnect sizer UP_M interface signals

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DTI interconnect register slice LPI_CG interface signals

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DTI interconnect register slice DN_S interface signals

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DTI interconnect register slice UP_S interface signals

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DTI interconnect register slice DN_M interface signals

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DTI interconnect register slice UP_M interface signals

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Invalidating TLBs and configuration caches

# metadata.contentDescription
This document describes the functionality and the effects of functional options on the behavior of the Arm CoreLink MMU-600AE System Memory Management Unit.