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Arm Corstone SSE-123 Example Subsystem Technical Reference Manual

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Arm® Corstone™ SSE-123 Example Subsystem Technical Reference Manual

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About IoT System on Chip implementations

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Advanced Microcontroller Bus Architecture (AMBA)

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Wakeup Interrupt Controller (WIC) and WIC-bridge

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Implementation Defined Attribution Unit (IDAU)

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SECDBGSTAT, Secure Debug Status register

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SCSECCTRL, System Control Security Control register

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GRETREG, General Purpose Retention register

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INITVTOR, Initial Secure Vector Table Offset register

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Secure privilege control registers block

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SPCSECCTRL, Secure Privilege Controller Secure Configuration Control register

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SECMPCINTSTATUS, Secure MPC Interrupt Status register

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SECPPCINTSTAT, Secure PPC Interrupt Status register

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SECPPCINTCLR, Secure PPC Interrupt Clear register

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SECPPCINTEN, Secure PPC Interrupt Enable register

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SECMSCINTSTAT, Secure MSC Interrupt Status register

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SECMSCINTCLR, Secure MSC Interrupt Clear register

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SECMSCINTEN, Secure MSC Interrupt Enable register

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BRGINTSTAT, Bridge Interrupt Status register

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BRGINTCLR, Bridge Interrupt Clear register

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BRGINTEN, Bridge Interrupt Enable register

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AHBNSPPCEXP, AHB Non-secure Access PPC Expansion register

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APBNSPPC, APB Non-secure Access PPC register

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APBNSPPCEXP0, APBNSPPCEXP1, APBNSPPCEXP2, and APBNSPPCEXP3, APB Non-secure Access PPC Expansion registers

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AHBSPPPCEXP, AHB Secure Privilege Access PPC Expansion register

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APBSPPPC, APB Secure Privilege Access PPC register

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APBSPPPCEXP0, APBSPPPCEXP1, APBSPPPCEXP2, and APBSPPPCEXP3, APB Secure Privilege Access PPC Expansion registers

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NSMSCEXP, Non-secure Access MSC Expansion register

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Non-secure privilege control registers block

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AHBNSPPPCEXP, AHB Non-secure Privilege Access PPC Expansion register

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APBNSPPPC, APB Non-secure Privilege Access PPC register

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APBNSPPPCEXP0, APBNSPPPCEXP1, APBNSPPPCEXP2, and APBNSPPPCEXP3, APB Non-Secure Privilege PPC Expansion registers

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Cortex-M23 processor Private Peripheral Bus (PPB)

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APB debug expansion master interface signals

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CNTSCR0, CNTSCR1, Counter Scaling registers

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CNTPIDR4, Peripheral Identification Register 4

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CNTPIDR0, Peripheral Identification Register 0

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CNTPIDR1, Peripheral Identification Register 1

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CNTPIDR2, Peripheral Identification Register 2

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CNTPIDR3, Peripheral Identification Register 3

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CNTCIDR0, Component Identification Register 0

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CNTCIDR1, Component Identification Register 1

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CNTCIDR2, Component Identification Register 2

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CNTCIDR3, Component Identification Register 3

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CNTPCT, Counter-timer Physical Count register

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CNTP_TVAL, Counter-timer Physical Timer TimerValue register

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CNTP_CTL, Counter-timer Physical Timer Control register

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CNTP_PID4, Peripheral Identification Register 4

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CNTP_PID0, Peripheral Identification Register 0

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CNTP_PID1, Peripheral Identification Register 1

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CNTP_PID2, Peripheral Identification Register 2

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CNTP_PID3, Peripheral Identification Register 3

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CNTP_CID0, Component Identification Register 0

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CNTP_CID1, Component Identification Register 1

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CNTP_CID2, Component Identification Register 2

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CNTP_CID3, Component Identification Register 3

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WCS, Watchdog Control and Status register

# metadata.contentDescription
This book is for the Corstone SSE-123 Example Subsystem.