# title
Arm Cortex-M55 Processor Technical Reference Manual

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Arm® Cortex®-M55 Processor Technical Reference Manual

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Security states, operation, and execution modes

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Cortex-M55 processor core registers summary

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Media and VFP Feature Register reset values, MVFR0, MVFR1, and MVFR2 reset values

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ICTR, Interrupt Controller Type Register

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DCAICLR and DCADCLR, Direct Cache Access Location Registers

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DCAICRR and DCADCRR, Direct Cache Access Read Registers

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IEBR0 and IEBR1, Instruction Cache Error Bank Register 0-1

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DEBR0 and DEBR1, Data Cache Error Bank Register 0-1

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TEBR0 and TEBR1, TCM Error Bank Register 0-1

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Data for TCU Error Bank Register 0-1, TEBRDATA0 and TEBRDATA1

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CPDLPSTATE, Core Power Domain Low Power State Register

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DPDLPSTATE, Debug Power Domain Low Power State Register

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CFGINFORD, Processor configuration information read data register

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ITCMCR and DTCMCR, TCM Control Registers

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ITGU_CTRL and DTGU_CTRL, ITGU and DTGU Control Registers

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ITGU_CFG and DTGU_CFG, ITGU and DTGU Configuration Registers

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ITGU_LUTn and DTGU_LUTn, ITGU and DTGU Look Up Table Registers

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EVENTMASKA and EVENTMASKn, n=0-14, Wakeup Event Mask Registers

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STLNVICPENDOR and STLNVICACTVOR, NVIC observation registers

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STLIDMPUSR, STLIMPUOR, STLD0MPUOR, and STLD1MPUOR, MPU observation registers

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Initializing the instruction and data cache

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Enabling the instruction and data cache 

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Enabling and locking the TCM security gates

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Operating mode transitions which change PDRAMS power state

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P-Channel interface tie-off when P-Channel is not used

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Debug Q-Channel and PDDEBUG power domain

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Access privilege level for Device and Normal memory

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IDAU interface and backwards compatibility

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Memory regions not controlled by SAU and IDAU

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Memory aliasing and IDAU/SAU configuration

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Access privilege level for Device and Normal memory

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High performance configuration M-AXI attributes and transactions

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Area optimized configuration M-AXI attributes and transactions

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Memory system implications for AXI accesses

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System access to TCM through the S-AHB DMA interface

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M-AXI and P-AHB interaction with the global exclusive monitor

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Cortex-M55 processor implementation of RAS

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Error processing in the L1 data and instruction cache

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Address decoder protection and white noise protection

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ERRFR0, RAS Error Record Feature Register

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ERRSTATUS0, RAS Error Record Primary Status Register

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ERRADDR0 and ERRADDR20, RAS Error Record Address Registers

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ERRMISC10, Error Record Miscellaneous Register 10

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ERRGSR0, RAS Fault Group Status Register

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ERRDEVID, RAS Error Record Device ID Register

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Registers associated with interrupt control and behavior

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Software Interrupt Generation register summary

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Debug access to coprocessor registers usage constraints

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Hazard between load and store instructions followed by coprocessor transactions

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Debugger actions for identifying the processor

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Processor ROM table identification and entries

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Debug identification block register summary

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Debugger access memory attributes and data cache access

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Debug during reset and before code execution commences

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ITM_ITCTRL, ITM Integration Mode Control Register

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CTI_INTACK, CTI Interrupt Acknowledge Register

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CTI_APPSET, CTI Application Channel Set Register

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CTI_APPCLR, CTI Application Channel Clear Register

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CTI_APPPULSE, CTI Application Channel Pulse Register

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CTI_INEN<n>, n=0-5, CTI Trigger <n> to Channel Enable Register

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CTI_OUTEN<n>, n=0-7, CTI Channel <n> to Trigger Enable Register

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CTI_TRIGINSTATUS, CTI Trigger Input Status Register

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CTI_TRIGOUTSTATUS, CTI Trigger Output Status Register

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CTI_CHINSTATUS, CTI Channel Input Status Register

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CTI_CHOUTSTATUS, CTI Channel Output Status Register

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CTI_CHANNELGATE, CTI Channel Gate Register

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CTI_ITCHOUT, Integration Test Channel Output Register

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CTI_ITTRIGOUT, Integration Test Trigger Output Register

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CTI_ITCHIN, Integration Test Channel Input Register

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CTI_ITTRIGIN, Integration Test Trigger Input Register

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CTI_ITCONTROL, Integration Mode Control Register

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CTI_DEVTYPE, Device Type Identifier Register

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CTI_PIDR4, Peripheral Identification Register 4

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CTI_PIDR5, Peripheral Identification Register 5

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CTI_PIDR6, Peripheral Identification Register 6

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CTI_PIDR7, Peripheral Identification Register 7

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CTI_PIDR0, Peripheral Identification Register 0

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CTI_PIDR1, Peripheral Identification Register 1

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CTI_PIDR2, Peripheral Identification Register 2

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CTI_PIDR3, Peripheral Identification Register 3

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CTI_ CIDR0, Component Identification Register 0

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CTI_ CIDR1, Component Identification Register 1

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CTI_ CIDR2, Component Identification Register 2

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CTI_ CIDR3, Component Identification Register 3

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EWIC_ASCR, EWIC Automatic Sequence Control Register

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EWIC_NUMID, EWIC Event Number ID Register

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EWIC_MASKA and EWIC_MASKn, EWIC Mask Registers

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EWIC_PENDA and EWIC_PENDn, EWIC Pend Event Registers

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EWIC_CLAIMSET, EWIC Claim Tag Set Register

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EWIC_CLAIMCLR, EWIC Claim Tag Clear Register

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TPIU_SSPSR, Supported Port Size Register

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TPIU_SPPR, Selected Pin Protocol Register

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TPIU_ACPR, Asynchronous Clock Prescaler Register

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TPIU_FFSR, Formatter and Flush Status Register

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TPIU_FFCR, Formatter and Flush Control Register

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ITFTTD0, Integration Test FIFO Test Data 0 Register

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ITATBCTR2, Integration Test ATB Control Register 2

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ITFTTD1, Integration Test FIFO Test Data 1 Register

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ITATBCTR0, Integration Test ATB Control 0 Register

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TPIU_DEVTYPE, Device Type Identifier Register

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TPIU_PIDR4, Peripheral Identification Register 4

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TPIU_PIDR5, Peripheral Identification Register 5

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TPIU_PIDR6, Peripheral Identification Register 6

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TPIU_PIDR7, Peripheral Identification Register 7

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TPIU_PIDR0, Peripheral Identification Register 0

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TPIU_PIDR1, Peripheral Identification Register 1

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TPIU_PIDR2, Peripheral Identification Register 2

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TPIU_PIDR3, Peripheral Identification Register 3

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TPIU_ CIDR0, Component Identification Register 0

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TPIU_ CIDR1, Component Identification Register 1

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TPIU_ CIDR2, Component Identification Register 2

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TPIU_ CIDR3, Component Identification Register 3

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Instruction Tightly Coupled Memory interface signals

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Data Tightly Coupled Memory interface signals

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P-Channel and Q-Channel power control signals

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Trace synchronization and trigger signals

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Use of instructions defined in architecture variants

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Use of Stack Pointer - as a general-purpose register R13 

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Register list in load and store multiple instructions

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UNPREDICTABLE instructions within an IT block

# metadata.contentDescription
This manual is for the Cortex -M55 processor. It provides reference information and contains programming details for registers. It also describes the memory system, the interrupts, the debug features, and other key features of the processor.