# title
Cycle Model Compiler User Guide Version 11.4

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Specifying the Verilog language variant to use when compiling

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Data collection in the Cycle Model Compiler

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Getting started with the Cycle Model Compiler

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Cycle Model Compiler command line options

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Options for troubleshooting design errors

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Passing directives to the Cycle Model Compiler

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Clock- and reset-related net control directives

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Dumping waveforms in different environments

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Using the Cycle Model API to dump waveforms

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Enabling waveform dumping in SystemC environments

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Improving speed by replacing DesignWare modules

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Using Profiling to find performance problems

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Locating the RTL source of a profiling hotspot

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Using Design Reducer to troubleshoot design errors

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Invoking the Design Reducer using the command line

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Invoking the Design Reducer using a command options file

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Defining errors to identify with the Check Design script

# metadata.contentDescription
Arm Cycle Models tools provide an integrated environment that places system validation in parallel with the hardware development flow. The Cycle Model Compiler takes an RTL hardware model and creates a high-performance linkable object, called the Cycle Model, that is cycle and register accurate. The Cycle Model provides an API for interfacing with your validation environment.