# title
Arm CoreSight System-on-Chip SoC-600 Technical Reference Manual

# topic.label
Arm® CoreSight™ System-on-Chip SoC-600 Technical Reference Manual

# topic.topics[].topics[].topics[].topics[].label
Valid combinations of AxCACHE and AxDOMAIN

# topic.topics[].topics[].topics[].topics[].label
Authentication signals and registers in a Memory Access Port

# topic.topics[].label
AMBA Trace Bus infrastructure components functional description

# topic.topics[].topics[].topics[].topics[].topics[].label
trigin input and ATB receiver interface trigger

# topic.topics[].topics[].topics[].topics[].label
Capturing trace after an event, and stopping

# topic.topics[].topics[].topics[].topics[].label
Only indicate triggers and continue to flush

# topic.topics[].label
Embedded Cross Trigger components functional description

# topic.topics[].topics[].topics[].label
Cortex-A5 PIL CoreSight component identification

# topic.topics[].topics[].topics[].label
Cortex-A8 PIL CoreSight component identification

# topic.topics[].topics[].topics[].label
Cortex-A9 PIL CoreSight component identification

# topic.topics[].topics[].topics[].label
Cortex-R4 PIL CoreSight component identification

# topic.topics[].topics[].topics[].label
Cortex-R5 PIL CoreSight component identification

# topic.topics[].topics[].topics[].label
Cortex-M0 PIL CoreSight component identification

# topic.topics[].topics[].topics[].label
Cortex-M3 PIL CoreSight component identification

# topic.topics[].topics[].topics[].label
Cortex-M4 PIL CoreSight component identification

# topic.topics[].topics[].topics[].label
css600_ahbap Direct Access Register 0, DAR0

# topic.topics[].topics[].topics[].label
css600_ahbap Direct Access Register 1, DAR1

# topic.topics[].topics[].topics[].label
css600_ahbap Direct Access Register 2, DAR2

# topic.topics[].topics[].topics[].label
css600_ahbap Direct Access Register 255, DAR255

# topic.topics[].topics[].topics[].label
css600_ahbap Control Status Word register, CSW

# topic.topics[].topics[].topics[].label
css600_ahbap Transfer Address Register, TAR

# topic.topics[].topics[].topics[].label
css600_ahbap Data Read/Write register, DRW

# topic.topics[].topics[].topics[].label
css600_ahbap Banked Data register 0, BD0

# topic.topics[].topics[].topics[].label
css600_ahbap Banked Data register 1, BD1

# topic.topics[].topics[].topics[].label
css600_ahbap Banked Data register 2, BD2

# topic.topics[].topics[].topics[].label
css600_ahbap Banked Data register 3, BD3

# topic.topics[].topics[].topics[].label
css600_ahbap Transfer Response Register, TRR

# topic.topics[].topics[].topics[].label
css600_ahbap Debug Base Address register, BASE

# topic.topics[].topics[].topics[].label
css600_ahbap Integration Test Status register, ITSTATUS

# topic.topics[].topics[].topics[].label
css600_ahbap Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_ahbap Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_ahbap Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_ahbap Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_ahbap Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_ahbap Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_ahbap Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_ahbap Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_ahbap Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_ahbap Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_ahbap Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_ahbap Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_ahbap Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_ahbap Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_ahbap Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_ahbap Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_apbap Direct Access Register 0, DAR0

# topic.topics[].topics[].topics[].label
css600_apbap Direct Access Register 1, DAR1

# topic.topics[].topics[].topics[].label
css600_apbap Direct Access Register 2, DAR2

# topic.topics[].topics[].topics[].label
css600_apbap Direct Access Register 255, DAR255

# topic.topics[].topics[].topics[].label
css600_apbap Control Status Word register, CSW

# topic.topics[].topics[].topics[].label
css600_apbap Transfer Address Register, TAR

# topic.topics[].topics[].topics[].label
css600_apbap Data Read/Write register, DRW

# topic.topics[].topics[].topics[].label
css600_apbap Banked Data register 0, BD0

# topic.topics[].topics[].topics[].label
css600_apbap Banked Data register 1, BD1

# topic.topics[].topics[].topics[].label
css600_apbap Banked Data register 2, BD2

# topic.topics[].topics[].topics[].label
css600_apbap Banked Data register 3, BD3

# topic.topics[].topics[].topics[].label
css600_apbap Transfer Response Register, TRR

# topic.topics[].topics[].topics[].label
css600_apbap Debug Base Address register, BASE

# topic.topics[].topics[].topics[].label
css600_apbap Integration Test Status register, ITSTATUS

# topic.topics[].topics[].topics[].label
css600_apbap Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_apbap Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_apbap Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_apbap Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_apbap Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_apbap Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_apbap Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_apbap Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_apbap Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_apbap Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_apbap Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_apbap Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_apbap Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_apbap Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_apbap Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_apbap Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_apbrom_32bit ROM Entries register 0, ROMEntry0

# topic.topics[].topics[].topics[].label
css600_apbrom_32bit ROM Entries register 1, ROMEntry1

# topic.topics[].topics[].topics[].label
css600_apbrom_32bit ROM Entries register 2, ROMEntry2

# topic.topics[].topics[].topics[].label
css600_apbrom_32bit ROM Entries register 511, ROMEntry511

# topic.topics[].topics[].topics[].label
css600_apbrom_64bit ROM Entries register 0, ROMEntry0

# topic.topics[].topics[].topics[].label
css600_apbrom_64bit ROM Entries register 0 bits [63:32], ROMEntry0HI

# topic.topics[].topics[].topics[].label
css600_apbrom_64bit ROM Entries register 1, ROMEntry1

# topic.topics[].topics[].topics[].label
css600_apbrom_64bit ROM Entries register 1 bits [63:32], ROMEntry1HI

# topic.topics[].topics[].topics[].label
css600_apbrom_64bit ROM Entries register 2, ROMEntry2

# topic.topics[].topics[].topics[].label
css600_apbrom_64bit ROM Entries register 2 bits [63:32], ROMEntry2HI

# topic.topics[].topics[].topics[].label
css600_apbrom_64bit ROM Entries register 255, ROMEntry255

# topic.topics[].topics[].topics[].label
css600_apbrom_64bit ROM Entries register 255 bits [63:32], ROMEntry255HI

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit ROM Entries register 0, ROMEntry0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit ROM Entries register 1, ROMEntry1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit ROM Entries register 2, ROMEntry2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit Debug Power Control Register 0, DBGPCR0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit Debug Power Control Register 1, DBGPCR1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit Debug Power Control Register 2, DBGPCR2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit Debug Power Control Register 31, DBGPCR31

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit Debug Power Status Register 0, DBGPSR0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit Debug Power Status Register 1, DBGPSR1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit Debug Power Status Register 2, DBGPSR2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit Debug Power Status Register 31, DBGPSR31

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit System Power Control Register 0, SYSPCR0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit System Power Control Register 1, SYSPCR1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit System Power Control Register 2, SYSPCR2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit System Power Control Register 31, SYSPCR31

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit System Power Status Register 0, SYSPSR0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit System Power Status Register 1, SYSPSR1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit System Power Status Register 2, SYSPSR2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit System Power Status Register 31, SYSPSR31

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_32bit Power Request ID Register, PRIDR0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit ROM Entries register 0, ROMEntry0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit ROM Entries register 0 bits [63:32], ROMEntry0HI

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit ROM Entries register 1, ROMEntry1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit ROM Entries register 1 bits [63:32], ROMEntry1HI

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit ROM Entries register 2, ROMEntry2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit ROM Entries register 2 bits [63:32], ROMEntry2HI

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit ROM Entries register 255 bits [63:32], ROMEntry255HI

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit Debug Power Control Register 0, DBGPCR0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit Debug Power Control Register 1, DBGPCR1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit Debug Power Control Register 2, DBGPCR2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit Debug Power Control Register 31, DBGPCR31

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit Debug Power Status Register 0, DBGPSR0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit Debug Power Status Register 1, DBGPSR1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit Debug Power Status Register 2, DBGPSR2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit Debug Power Status Register 31, DBGPSR31

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit System Power Control Register 0, SYSPCR0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit System Power Control Register 1, SYSPCR1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit System Power Control Register 2, SYSPCR2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit System Power Control Register 31, SYSPCR31

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit System Power Status Register 0, SYSPSR0

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit System Power Status Register 1, SYSPSR1

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit System Power Status Register 2, SYSPSR2

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit System Power Status Register 31, SYSPSR31

# topic.topics[].topics[].topics[].label
css600_apbrom_gpr_64bit Power Request ID Register, PRIDR0

# topic.topics[].topics[].topics[].label
css600_apv1adapter Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_apv1adapter Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_apv1adapter Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_apv1adapter Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_atbfunnel_prog Integration test control register 3, ITATBCTR3

# topic.topics[].topics[].topics[].label
css600_atbfunnel_prog Integration test control register 2, ITATBCTR2

# topic.topics[].topics[].topics[].label
css600_atbfunnel_prog Integration test control register 1, ITATBCTR1

# topic.topics[].topics[].topics[].label
css600_atbfunnel_prog Integration test control register 0, ITATBCTR0

# topic.topics[].topics[].topics[].label
css600_atbfunnel_prog Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_atbfunnel_prog Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_atbfunnel_prog Device Affinity register 0, DEVAFF0

# topic.topics[].topics[].topics[].label
css600_atbfunnel_prog Device Affinity register 1, DEVAFF1

# topic.topics[].topics[].topics[].label
css600_atbreplicator_prog ID filtering control 0 register, IDFILT0

# topic.topics[].topics[].topics[].label
css600_atbreplicator_prog ID filtering control 1 register, IDFILT1

# topic.topics[].topics[].topics[].label
css600_atbreplicator_prog Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_atbreplicator_prog Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_axiap Direct Access Register 0, DAR0

# topic.topics[].topics[].topics[].label
css600_axiap Direct Access Register 1, DAR1

# topic.topics[].topics[].topics[].label
css600_axiap Direct Access Register 2, DAR2

# topic.topics[].topics[].topics[].label
css600_axiap Direct Access Register 255, DAR255

# topic.topics[].topics[].topics[].label
css600_axiap Control Status Word register, CSW

# topic.topics[].topics[].topics[].label
css600_axiap Transfer Address Register, TAR

# topic.topics[].topics[].topics[].label
css600_axiap Transfer Address Register, TARH

# topic.topics[].topics[].topics[].label
css600_axiap Data Read/Write register, DRW

# topic.topics[].topics[].topics[].label
css600_axiap Banked Data register 0, BD0

# topic.topics[].topics[].topics[].label
css600_axiap Banked Data register 1, BD1

# topic.topics[].topics[].topics[].label
css600_axiap Banked Data register 2, BD2

# topic.topics[].topics[].topics[].label
css600_axiap Banked Data register 3, BD3

# topic.topics[].topics[].topics[].label
css600_axiap Transfer Response Register, TRR

# topic.topics[].topics[].topics[].label
css600_axiap Memory Encryption Contexts Register, MECID

# topic.topics[].topics[].topics[].label
css600_axiap Configuration Register 1, CFG1

# topic.topics[].topics[].topics[].label
css600_axiap Debug Base Address register upper 32 bits, BASEH

# topic.topics[].topics[].topics[].label
css600_axiap Debug Base Address register, BASE

# topic.topics[].topics[].topics[].label
css600_axiap Integration Test Status register, ITSTATUS

# topic.topics[].topics[].topics[].label
css600_axiap Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_axiap Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_axiap Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_axiap Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_axiap Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_axiap Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_axiap Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_axiap Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_axiap Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_axiap Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_axiap Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_axiap Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_axiap Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_axiap Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_axiap Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_axiap Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_axiap_mte Direct Access Register 0, DAR0

# topic.topics[].topics[].topics[].label
css600_axiap_mte Direct Access Register 1, DAR1

# topic.topics[].topics[].topics[].label
css600_axiap_mte Direct Access Register 2, DAR2

# topic.topics[].topics[].topics[].label
css600_axiap_mte Direct Access Register 255, DAR255

# topic.topics[].topics[].topics[].label
css600_axiap_mte Control Status Word register, CSW

# topic.topics[].topics[].topics[].label
css600_axiap_mte Transfer Address Register, TAR

# topic.topics[].topics[].topics[].label
css600_axiap_mte Transfer Address Register, TARH

# topic.topics[].topics[].topics[].label
css600_axiap_mte Data Read/Write register, DRW

# topic.topics[].topics[].topics[].label
css600_axiap_mte Banked Data register 0, BD0

# topic.topics[].topics[].topics[].label
css600_axiap_mte Banked Data register 1, BD1

# topic.topics[].topics[].topics[].label
css600_axiap_mte Banked Data register 2, BD2

# topic.topics[].topics[].topics[].label
css600_axiap_mte Banked Data register 3, BD3

# topic.topics[].topics[].topics[].label
css600_axiap_mte Transfer Response Register, TRR

# topic.topics[].topics[].topics[].label
css600_axiap_mte Tag 0 Transfer Register, T0TR

# topic.topics[].topics[].topics[].label
css600_axiap_mte Memory Encryption Contexts Register, MECID

# topic.topics[].topics[].topics[].label
css600_axiap_mte Configuration Register 1, CFG1

# topic.topics[].topics[].topics[].label
css600_axiap_mte Debug Base Address register upper 32 bits, BASEH

# topic.topics[].topics[].topics[].label
css600_axiap_mte Debug Base Address register, BASE

# topic.topics[].topics[].topics[].label
css600_axiap_mte Integration Test Status register, ITSTATUS

# topic.topics[].topics[].topics[].label
css600_axiap_mte Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_axiap_mte Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_axiap_mte Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_axiap_mte Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_axiap_mte Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_axiap_mte Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_axiap_mte Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_axiap_mte Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_axiap_mte Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_axiap_mte Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_axiap_mte Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_axiap_mte Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_axiap_mte Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_axiap_mte Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_axiap_mte Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_axiap_mte Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_catu CATU control register, CONTROL

# topic.topics[].topics[].topics[].label
css600_catu AXI control register, AXICTRL

# topic.topics[].topics[].topics[].label
css600_catu Interrupt enable register, IRQEN

# topic.topics[].topics[].topics[].label
css600_catu Scatter List Address Low register, SLADDRLO

# topic.topics[].topics[].topics[].label
css600_catu Scatter List Address High register, SLADDRHI

# topic.topics[].topics[].topics[].label
css600_catu Input Address Low register, INADDRLO

# topic.topics[].topics[].topics[].label
css600_catu Input Address High register, INADDRHI

# topic.topics[].topics[].topics[].label
css600_catu Integration Test Interrupt register, ITIRQ

# topic.topics[].topics[].topics[].label
css600_catu Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_catu Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_catu Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_catu Device Configuration Register, DEVID

# topic.topics[].topics[].topics[].label
css600_catu Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_catu Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_catu Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_catu Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_catu Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_catu Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_catu Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_catu Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_catu Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_catu Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_catu Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_catu Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_catu Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_cti CTI Control register, CTICONTROL

# topic.topics[].topics[].topics[].label
css600_cti CTI Interrupt Acknowledge register, CTIINTACK

# topic.topics[].topics[].topics[].label
css600_cti CTI Application Channel Set register, CTIAPPSET

# topic.topics[].topics[].topics[].label
css600_cti CTI Application Channel Clear register, CTIAPPCLEAR

# topic.topics[].topics[].topics[].label
css600_cti CTI Application Channel Pulse register, CTIAPPPULSE

# topic.topics[].topics[].topics[].label
css600_cti CTI Trigger 0 to Channel Enable register, CTIINEN0

# topic.topics[].topics[].topics[].label
css600_cti CTI Trigger 1 to Channel Enable register, CTIINEN1

# topic.topics[].topics[].topics[].label
css600_cti CTI Trigger 2 to Channel Enable register, CTIINEN2

# topic.topics[].topics[].topics[].label
css600_cti CTI Channel to Trigger 0 Enable register, CTIOUTEN0

# topic.topics[].topics[].topics[].label
css600_cti CTI Channel to Trigger 1 Enable register, CTIOUTEN1

# topic.topics[].topics[].topics[].label
css600_cti CTI Channel to Trigger 2 Enable register, CTIOUTEN2

# topic.topics[].topics[].topics[].label
css600_cti CTI Channel to Trigger 31 Enable register, CTIOUTEN31

# topic.topics[].topics[].topics[].label
css600_cti CTI Trigger Input Status register, CTITRIGINSTATUS

# topic.topics[].topics[].topics[].label
css600_cti CTI Trigger Output Status register, CTITRIGOUTSTATUS

# topic.topics[].topics[].topics[].label
css600_cti CTI Channel Input Status register, CTICHINSTATUS

# topic.topics[].topics[].topics[].label
css600_cti CTI Channel Output Status register, CTICHOUTSTATUS

# topic.topics[].topics[].topics[].label
css600_cti Enable CTI Channel Gate register, CTIGATE

# topic.topics[].topics[].topics[].label
css600_cti External Multiplexer Control register, ASICCTRL

# topic.topics[].topics[].topics[].label
css600_cti Integration Test Channel Output register, ITCHOUT

# topic.topics[].topics[].topics[].label
css600_cti Integration Test Trigger Output register, ITTRIGOUT

# topic.topics[].topics[].topics[].label
css600_cti Integration Test Channel Input register, ITCHIN

# topic.topics[].topics[].topics[].label
css600_cti Integration Test Trigger Input register, ITTRIGIN

# topic.topics[].topics[].topics[].label
css600_cti Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_cti Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_cti Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_cti Device Affinity register 0, DEVAFF0

# topic.topics[].topics[].topics[].label
css600_cti Device Affinity register 1, DEVAFF1

# topic.topics[].topics[].topics[].label
css600_cti Device Architecture Register, DEVARCH

# topic.topics[].topics[].topics[].label
css600_cti Device Configuration Register, DEVID

# topic.topics[].topics[].topics[].label
css600_cti Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_cti Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_cti Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_cti Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_cti Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_cti Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_cti Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_cti Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_cti Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_cti Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_cti Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_cti Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_cti Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_dp Debug Port Identification Register, DPIDR

# topic.topics[].topics[].topics[].label
css600_dp Debug Port Identification Register 1, DPIDR1

# topic.topics[].topics[].topics[].label
css600_dp Base Pointer Register 0, BASEPTR0

# topic.topics[].topics[].topics[].label
css600_dp Base Pointer Register 1, BASEPTR1

# topic.topics[].topics[].topics[].label
css600_dp Data Link Control Register, DLCR

# topic.topics[].topics[].topics[].label
css600_dp Data Link Protocol Identification Register, DLPIDR

# topic.topics[].topics[].topics[].label
css600_dp Event Status Register, EVENTSTAT

# topic.topics[].topics[].topics[].label
css600_dp Target Selection Register, TARGETSEL

# topic.topics[].topics[].topics[].label
css600_jtagap Control/Status Word register, CSW

# topic.topics[].topics[].topics[].label
css600_jtagap Port Select register, PSEL

# topic.topics[].topics[].topics[].label
css600_jtagap Port Status register, PSTA

# topic.topics[].topics[].topics[].label
css600_jtagap Byte FIFO Register 1, BFIFO1

# topic.topics[].topics[].topics[].label
css600_jtagap Byte FIFO Register 2, BFIFO2

# topic.topics[].topics[].topics[].label
css600_jtagap Byte FIFO Register 3, BFIFO3

# topic.topics[].topics[].topics[].label
css600_jtagap Byte FIFO Register 4, BFIFO4

# topic.topics[].topics[].topics[].label
css600_jtagap Integration Test Status register, ITSTATUS

# topic.topics[].topics[].topics[].label
css600_jtagap Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_jtagap Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_jtagap Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_jtagap Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_jtagap Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_jtagap Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_jtagap Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_jtagap Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_jtagap Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_jtagap Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_jtagap Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_jtagap Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_jtagap Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_jtagap Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_jtagap Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_jtagap Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_tmc_etb RAM Read Data register, RRD

# topic.topics[].topics[].topics[].label
css600_tmc_etb RAM Read Pointer register, RRP

# topic.topics[].topics[].topics[].label
css600_tmc_etb RAM Write Pointer register, RWP

# topic.topics[].topics[].topics[].label
css600_tmc_etb Trigger Counter register, TRG

# topic.topics[].topics[].topics[].label
css600_tmc_etb RAM Write Data register, RWD

# topic.topics[].topics[].topics[].label
css600_tmc_etb Latched Buffer Fill Level, LBUFLEVEL

# topic.topics[].topics[].topics[].label
css600_tmc_etb Current Buffer Fill Level, CBUFLEVEL

# topic.topics[].topics[].topics[].label
css600_tmc_etb Buffer Level Water Mark, BUFWM

# topic.topics[].topics[].topics[].label
css600_tmc_etb Formatter and Flush Status Register, FFSR

# topic.topics[].topics[].topics[].label
css600_tmc_etb Formatter and Flush Control Register, FFCR

# topic.topics[].topics[].topics[].label
css600_tmc_etb Integration Test Event and Interrupt Control Register, ITEVTINTR

# topic.topics[].topics[].topics[].label
css600_tmc_etb Integration Test Trigger In and Flush In register, ITTRFLIN

# topic.topics[].topics[].topics[].label
css600_tmc_etb Integration Test ATB Data 0 Register, ITATBDATA0

# topic.topics[].topics[].topics[].label
css600_tmc_etb Integration Test ATB Control 2 Register, ITATBCTR2

# topic.topics[].topics[].topics[].label
css600_tmc_etb Integration Test ATB Control 1 Register, ITATBCTR1

# topic.topics[].topics[].topics[].label
css600_tmc_etb Integration Test ATB Control 0 Register, ITATBCTR0

# topic.topics[].topics[].topics[].label
css600_tmc_etb Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_tmc_etb Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_tmc_etb Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_tmc_etb Device Configuration Register 1, DEVID1

# topic.topics[].topics[].topics[].label
css600_tmc_etb Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_tmc_etb Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_tmc_etb Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_tmc_etb Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_tmc_etb Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_tmc_etb Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_tmc_etb Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_tmc_etb Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_tmc_etb Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_tmc_etb Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_tmc_etb Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_tmc_etb Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_tmc_etb Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_tmc_etf RAM Read Data register, RRD

# topic.topics[].topics[].topics[].label
css600_tmc_etf RAM Read Pointer register, RRP

# topic.topics[].topics[].topics[].label
css600_tmc_etf RAM Write Pointer register, RWP

# topic.topics[].topics[].topics[].label
css600_tmc_etf Trigger Counter register, TRG

# topic.topics[].topics[].topics[].label
css600_tmc_etf RAM Write Data register, RWD

# topic.topics[].topics[].topics[].label
css600_tmc_etf Latched Buffer Fill Level, LBUFLEVEL

# topic.topics[].topics[].topics[].label
css600_tmc_etf Current Buffer Fill Level, CBUFLEVEL

# topic.topics[].topics[].topics[].label
css600_tmc_etf Buffer Level Water Mark, BUFWM

# topic.topics[].topics[].topics[].label
css600_tmc_etf Formatter and Flush Status Register, FFSR

# topic.topics[].topics[].topics[].label
css600_tmc_etf Formatter and Flush Control Register, FFCR

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test ATB Transmitter Data 0 register, ITATBMDATA0

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test ATB Transmitter Control 2 register, ITATBMCTR2

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test ATB Transmitter Control 1 register, ITATBMCTR1

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test ATB Transmitter Control 0 register, ITATBMCTR0

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test Event and Interrupt Control Register, ITEVTINTR

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test Trigger In and Flush In register, ITTRFLIN

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test ATB Data 0 Register, ITATBDATA0

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test ATB Control 2 Register, ITATBCTR2

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test ATB Control 1 Register, ITATBCTR1

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Test ATB Control 0 Register, ITATBCTR0

# topic.topics[].topics[].topics[].label
css600_tmc_etf Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_tmc_etf Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_tmc_etf Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_tmc_etf Device Configuration Register 1, DEVID1

# topic.topics[].topics[].topics[].label
css600_tmc_etf Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_tmc_etf Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_tmc_etf Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_tmc_etf Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_tmc_etf Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_tmc_etf Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_tmc_etf Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_tmc_etf Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_tmc_etf Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_tmc_etf Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_tmc_etf Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_tmc_etf Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_tmc_etf Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_tmc_etr RAM Read Data register, RRD

# topic.topics[].topics[].topics[].label
css600_tmc_etr RAM Read Pointer register, RRP

# topic.topics[].topics[].topics[].label
css600_tmc_etr RAM Write Pointer register, RWP

# topic.topics[].topics[].topics[].label
css600_tmc_etr Trigger Counter register, TRG

# topic.topics[].topics[].topics[].label
css600_tmc_etr RAM Write Data register, RWD

# topic.topics[].topics[].topics[].label
css600_tmc_etr Latched Buffer Fill Level, LBUFLEVEL

# topic.topics[].topics[].topics[].label
css600_tmc_etr Current Buffer Fill Level, CBUFLEVEL

# topic.topics[].topics[].topics[].label
css600_tmc_etr Buffer Level Water Mark, BUFWM

# topic.topics[].topics[].topics[].label
css600_tmc_etr RAM Read Pointer High register, RRPHI

# topic.topics[].topics[].topics[].label
css600_tmc_etr RAM Write Pointer High register, RWPHI

# topic.topics[].topics[].topics[].label
css600_tmc_etr AXI Control Register, AXICTL

# topic.topics[].topics[].topics[].label
css600_tmc_etr Data Buffer Address Low register, DBALO

# topic.topics[].topics[].topics[].label
css600_tmc_etr Data Buffer Address HIGH register, DBAHI

# topic.topics[].topics[].topics[].label
css600_tmc_etr RAM Update Read Pointer register, RURP

# topic.topics[].topics[].topics[].label
css600_tmc_etr Formatter and Flush Status Register, FFSR

# topic.topics[].topics[].topics[].label
css600_tmc_etr Formatter and Flush Control Register, FFCR

# topic.topics[].topics[].topics[].label
css600_tmc_etr AXI Control Register 1, AXICTL1

# topic.topics[].topics[].topics[].label
css600_tmc_etr Integration Test Event and Interrupt Control Register, ITEVTINTR

# topic.topics[].topics[].topics[].label
css600_tmc_etr Integration Test Trigger In and Flush In register, ITTRFLIN

# topic.topics[].topics[].topics[].label
css600_tmc_etr Integration Test ATB Data 0 Register, ITATBDATA0

# topic.topics[].topics[].topics[].label
css600_tmc_etr Integration Test ATB Control 2 Register, ITATBCTR2

# topic.topics[].topics[].topics[].label
css600_tmc_etr Integration Test ATB Control 1 Register, ITATBCTR1

# topic.topics[].topics[].topics[].label
css600_tmc_etr Integration Test ATB Control 0 Register, ITATBCTR0

# topic.topics[].topics[].topics[].label
css600_tmc_etr Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_tmc_etr Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_tmc_etr Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_tmc_etr Device Configuration Register 1, DEVID1

# topic.topics[].topics[].topics[].label
css600_tmc_etr Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_tmc_etr Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_tmc_etr Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_tmc_etr Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_tmc_etr Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_tmc_etr Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_tmc_etr Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_tmc_etr Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_tmc_etr Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_tmc_etr Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_tmc_etr Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_tmc_etr Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_tmc_etr Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_tmc_ets RAM Read Data register, RRD

# topic.topics[].topics[].topics[].label
css600_tmc_ets Trigger Counter register, TRG

# topic.topics[].topics[].topics[].label
css600_tmc_ets Formatter and Flush Status Register, FFSR

# topic.topics[].topics[].topics[].label
css600_tmc_ets Formatter and Flush Control Register, FFCR

# topic.topics[].topics[].topics[].label
css600_tmc_ets Integration Test Event and Interrupt Control Register, ITEVTINTR

# topic.topics[].topics[].topics[].label
css600_tmc_ets Integration Test Trigger In and Flush In register, ITTRFLIN

# topic.topics[].topics[].topics[].label
css600_tmc_ets Integration Test ATB Data 0 Register, ITATBDATA0

# topic.topics[].topics[].topics[].label
css600_tmc_ets Integration Test ATB Control 2 Register, ITATBCTR2

# topic.topics[].topics[].topics[].label
css600_tmc_ets Integration Test ATB Control 1 Register, ITATBCTR1

# topic.topics[].topics[].topics[].label
css600_tmc_ets Integration Test ATB Control 0 Register, ITATBCTR0

# topic.topics[].topics[].topics[].label
css600_tmc_ets Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_tmc_ets Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_tmc_ets Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_tmc_ets Device Configuration Register 1, DEVID1

# topic.topics[].topics[].topics[].label
css600_tmc_ets Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_tmc_ets Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_tmc_ets Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_tmc_ets Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_tmc_ets Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_tmc_ets Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_tmc_ets Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_tmc_ets Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_tmc_ets Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_tmc_ets Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_tmc_ets Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_tmc_ets Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_tmc_ets Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_tpiu Supported Port Size Register, SSPSR

# topic.topics[].topics[].topics[].label
css600_tpiu Current Port Size Register, CSPSR

# topic.topics[].topics[].topics[].label
css600_tpiu Supported Trigger Modes Register, STMR

# topic.topics[].topics[].topics[].label
css600_tpiu Trigger Counter Value Register, TCVR

# topic.topics[].topics[].topics[].label
css600_tpiu Trigger Counter Multiplier Register, TCMR

# topic.topics[].topics[].topics[].label
css600_tpiu Supported Test Patterns/Modes Register, STPMR

# topic.topics[].topics[].topics[].label
css600_tpiu Current Test Patterns/Modes Register, CTPMR

# topic.topics[].topics[].topics[].label
css600_tpiu Test Pattern Repeat Counter Register, TPRCR

# topic.topics[].topics[].topics[].label
css600_tpiu Formatter and Flush Status Register, FFSR

# topic.topics[].topics[].topics[].label
css600_tpiu Formatter and Flush Control Register, FFCR

# topic.topics[].topics[].topics[].label
css600_tpiu Formatter Synchronization Count Register, FSCR

# topic.topics[].topics[].topics[].label
css600_tpiu External Control Port In Register, EXTCTLIN

# topic.topics[].topics[].topics[].label
css600_tpiu External Control Port Out Register, EXTCTLOUT

# topic.topics[].topics[].topics[].label
css600_tpiu Integration Test Trigger In and Flush In Register, ITTRFLIN

# topic.topics[].topics[].topics[].label
css600_tpiu Integration Test ATB Data Register 0, ITATBDATA0

# topic.topics[].topics[].topics[].label
css600_tpiu Integration Test ATB Control Register 2, ITATBCTR2

# topic.topics[].topics[].topics[].label
css600_tpiu Integration Test ATB Control Register 1, ITATBCTR1

# topic.topics[].topics[].topics[].label
css600_tpiu Integration Test ATB Control Register 0, ITATBCTR0

# topic.topics[].topics[].topics[].label
css600_tpiu Integration Test Output Control Register, ITOUTCTR

# topic.topics[].topics[].topics[].label
css600_tpiu Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_tpiu Claim Tag Set Register, CLAIMSET

# topic.topics[].topics[].topics[].label
css600_tpiu Claim Tag Clear Register, CLAIMCLR

# topic.topics[].topics[].topics[].label
css600_tpiu Device Configuration Register, DEVID

# topic.topics[].topics[].topics[].label
css600_tpiu Device Type Identifier Register, DEVTYPE

# topic.topics[].topics[].topics[].label
css600_tpiu Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_tpiu Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_tpiu Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_tpiu Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_tpiu Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_tpiu Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_tpiu Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_tpiu Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_tpiu Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_tpiu Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_tpiu Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_tpiu Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_tsgen Counter Control Register, CNTCR

# topic.topics[].topics[].topics[].label
css600_tsgen Counter Status Register, CNTSR

# topic.topics[].topics[].topics[].label
css600_tsgen Current value of Counter[31:0], CNTCVL

# topic.topics[].topics[].topics[].label
css600_tsgen Current value of Counter[63:32], CNTCVU

# topic.topics[].topics[].topics[].label
css600_tsgen Base Frequency ID register, CNTFID0

# topic.topics[].topics[].topics[].label
css600_tsgen Integration Test Status Register, ITSTAT

# topic.topics[].topics[].topics[].label
css600_tsgen Integration Mode Control Register, ITCTRL

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_tsgen Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_tsgen Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_tsgen Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_tsgen Component Identification Register 3, CIDR3

# topic.topics[].topics[].topics[].label
css600_tsgen Current value of Counter[31:0], CNTCVLREAD

# topic.topics[].topics[].topics[].label
css600_tsgen Current value of Counter[63:32], CNTCVUREAD

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 4, PIDR4

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 5, PIDR5

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 6, PIDR6

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 7, PIDR7

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 0, PIDR0

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 1, PIDR1

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 2, PIDR2

# topic.topics[].topics[].topics[].label
css600_tsgen Peripheral Identification Register 3, PIDR3

# topic.topics[].topics[].topics[].label
css600_tsgen Component Identification Register 0, CIDR0

# topic.topics[].topics[].topics[].label
css600_tsgen Component Identification Register 1, CIDR1

# topic.topics[].topics[].topics[].label
css600_tsgen Component Identification Register 2, CIDR2

# topic.topics[].topics[].topics[].label
css600_tsgen Component Identification Register 3, CIDR3

# metadata.contentDescription
This book is for the Arm CoreSight SoC-600.