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Arm CoreSight SoC-400 Technical Reference Manual

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Arm® CoreSight™ SoC-400 Technical Reference Manual

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Granular Power Requester register summary

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Debug Power Acknowledge register, CPWRUPACK

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Integration Mode Control register, ITCTRL

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Device Type Identifier register, DEVTYPE

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Integration Test ATB Data0 register, ITATBDATA0

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Integration Test ATB Control 1 Register, ITATBCTR1

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Integration Test ATB Control 0 Register, ITATBCTR0

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Integration Mode Control register, ITCTRL

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Device Type Identifier register, DEVTYPE

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ID filtering for ATB master port 0, IDFILTER0

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ID filtering for ATB master port 1, IDFILTER1

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Integration Mode ATB Control 0 Register, ITATBCTR0

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Integration Mode ATB Control 1 Register, ITATBCTR1

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Integration Mode Control register, ITCTRL

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Device Type Identifier register, DEVTYPE

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ETB Formatter and Flush Status Register, FFSR

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ETB Formatter and Flush Control Register, FFCR

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Integration Test Miscellaneous Output register 0, ITMISCOP0

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Integration Test Trigger In and Flush In Acknowledge register, ITTRFLINACK

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Integration Test Trigger In and Flush In register, ITTRFLIN

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Integration Test ATB Data register 0, ITATBDATA0

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Integration Test ATB Control Register 2, ITATBCTR2

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Integration Test ATB Control Register 1, ITATBCTR1

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Integration Test ATB Control Register 0, ITATBCTR0

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Integration Mode Control register, ITCTRL

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Device Type Identifier register, DEVTYPE

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Current Port Size register, Current_port_size

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TPIU Test Pattern Repeat Counter Register, TPRCR

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Formatter and Flush Status Register, FFSR

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Formatter and Flush Control Register, FFCR

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Formatter Synchronization Counter Register, FSCR

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TPIU EXCTL In Port register, EXTCTL_In_Port

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TPIU EXCTL Out Port register, EXTCTL_Out_Port

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Integration Test Trigger In and Flush In Acknowledge register, ITTRFLINACK

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Integration Test Trigger In and Flush In register, ITTRFLIN

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Integration Test ATB Data register 0, ITATBDATA0

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Integration Test ATB Control Register 2, ITATBCTR2

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Integration Test ATB Control Register 1, ITATBCTR1

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Integration Test ATB Control Register 0, ITATBCTR0

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Integration Mode Control register, ITCTRL

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Device Type Identifier register, DEVTYPE

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CTI Interrupt Acknowledge register, CTIINTACK

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CTI Application Trigger Set register, CTIAPPSET

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CTI Application Trigger Clear register, CTIAPPCLEAR

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CTI Application Pulse register, CTIAPPPULSE

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CTI Trigger 0 to Channel Enable register, CTIINEN0

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CTI Trigger 1 to Channel Enable register, CTIINEN1

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CTI Trigger 2 to Channel Enable register, CTIINEN2

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CTI Trigger 3 to Channel Enable register, CTIINEN3

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CTI Trigger 4 to Channel Enable register, CTIINEN4

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CTI Trigger 5 to Channel Enable register, CTIINEN5

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CTI Trigger 6 to Channel Enable register, CTIINEN6

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CTI Trigger 7 to Channel Enable register, CTIINEN7

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CTI Channel to Trigger 0 Enable register, CTIOUTEN0

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CTI Channel to Trigger 1 Enable register, CTIOUTEN1

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CTI Channel to Trigger 2 Enable register, CTIOUTEN2

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CTI Channel to Trigger 3 Enable register, CTIOUTEN3

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CTI Channel to Trigger 4 Enable register, CTIOUTEN4

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CTI Channel to Trigger 5 Enable register, CTIOUTEN5

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CTI Channel to Trigger 6 Enable register, CTIOUTEN6

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CTI Channel to Trigger 7 Enable register, CTIOUTEN7

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CTI Trigger In Status register, CTITRIGINSTATUS

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CTI Trigger Out Status register, CTITRIGOUTSTATUS

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CTI Channel In Status register, CTICHINSTATUS

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CTI Channel Out Status register, CTICHOUTSTATUS

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Enable CTI Channel Gate register, CTIGATE

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External Multiplexer Control register, ASICCTL

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Integration Test Channel Input Acknowledge register, ITCHINACK

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Integration Test Trigger Input Acknowledge register, ITTRIGINACK

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Integration Test Channel Output register, ITCHOUT

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Integration Test Trigger Output register, ITTRIGOUT

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Integration Test Channel Output Acknowledge register, ITCHOUTACK

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Integration Test Trigger Output Acknowledge register, ITTRIGOUTACK

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Integration Test Channel Input register, ITCHIN

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Integration Test Trigger Input register, ITTRIGIN

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Integration Mode Control register, ITCTRL

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Device Type Identifier register, DEVTYPE

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JTAG-AP Control/Status Word register, CSW, 0x00

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JTAG-AP Port Select register, PORTSEL, 0x04

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JTAG-AP Port Status register, PSTA, 0x08

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JTAG-AP Byte FIFO registers, BFIFOn, 0x10-0x1C

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AHB-AP Control/Status Word register, CSW, 0x00

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AHB-AP Transfer Address Register, TAR, 0x04

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AHB-AP Data Read/Write register, DRW, 0x0C

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AHB-AP Banked Data registers, BD0-BD03, 0x10-0x1C

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AHB-AP Debug Base Address register, BASE, 0xF8

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AHB-AP Identification Register, IDR, 0xFC

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AXI-AP Debug Base Address register, BASE [63:32]

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AXI-AP Debug Base Address register, BASE [31:0]

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APB-AP Control/Status Word register, CSW, 0x00

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APB-AP Transfer Address Register, TAR, 0x04

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APB-AP Data Read/Write register, DRW, 0x0C

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APB-AP Banked Data registers, BD0-BD3, 0x10-0x1C

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APB-AP Debug Base Address register, BASE, 0xF8

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Debug Port Identification Register, DPIDR

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Read Buffer implementation and use on a JTAG-DP

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Read Buffer implementation and use on an SW-DP

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Data Link Control Register, DLCR (SW-DP only)

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Turnaround tristate period, TURANROUND, bits [9:8]

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Wire operating mode, WIREMODE, bits [7:6]

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Target Identification register, TARGETID (SW-DP only)

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Data Link Protocol Identification Register, DLPIDR (SW-DP only)

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Read Resend register, RESEND (SW-DP only)

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Timestamp generator register summary table

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Current Counter Value Lower register, CNTCVL

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Current Counter Value Upper register, CNTCVU

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Common debug port features and registers

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Example use of pushed verify operation on an AHB-AP

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Example use of pushed find operation on an AHB-AP

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Valid combinations of AxCACHE and AxDOMAIN table

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Interfacing an AHB5 slave to the cxdapahbap

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Differentiation between system and access port initiated error responses

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Capturing trace after an event and stopping

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Only indicating triggers and continuing to flush

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Narrow timestamp asynchronous bridge signals

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Narrow timestamp synchronous bridge signals

# metadata.contentDescription
ARM CoreSight SoC-400 Technical Reference Manual (TRM). This book describes how to incorporate CoreSight System Components into designs, and produce real-time instruction and data trace information from a SoC.