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ARM Cortex-A9 Technical Reference Manual r4p1

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ARM Cortex-A9 Technical Reference Manual

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Program Flow Trace and Program Trace Macrocell

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CP15 system control registers grouped by CRn order

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CP15 system control registers grouped by function

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Preload Engine User Accessibility Register

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Preload Engine Parameters Control Register

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Jazelle Operating System Control Register

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Jazelle Configurable Opcode Translation Table Register

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About the L1 instruction side memory system

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Cortex-A9 behavior for Normal Memory Cacheable memory regions

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AXI master 0 interface and AXI master 1 interface attributes

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Optimized accesses to the L2 memory interface

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Prefetch hint to the L2 memory interface

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AXI Master1 signals instruction accesses

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MBIST signals with parity support implemented

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MBIST signals without parity support implemented

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Single load and store operation cycle timings

# metadata.contentDescription
ARM Cortex-A9 Technical Reference Manual (TRM) describes the uniprocessor version of the Cortex-A9 processor including the optional Preload Engine. A guide to the registers, instructions, caches, memory, and memory interfaces.