# title
ARM Cortex-A9 MPCore Technical Reference Manual r4p1

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ARM Cortex-A9 MPCore Technical Reference Manual

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SCU Invalidate All Registers in Secure State Register

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Event communication with an external agent using WFE/SEV

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Cortex-A9 MPCore 1-N interrupt model handling

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Global timer, private timers, and watchdog registers

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About the private timer and watchdog blocks

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Private timer and watchdog register summary

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Global Timer Counter Registers, 0x00 and 0x04

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Comparator Value Registers, 0x10 and 0x14

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Individual processor power-on SIMD MPE reset

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Individual processor watchdog flag reset

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Individual Cortex-A9 processor power management

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Communication to the Power Management Controller

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Cortex-A9 MPCore APB Debug interface and memory map

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Configuration for a single Cortex-A9 processor

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Configuration for two Cortex-A9 processors

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Configuration for three Cortex-A9 processors

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Configuration for four Cortex-A9 processors

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MBIST interface signals with parity support

# metadata.contentDescription
This book is for the Cortex-A9 MPCore. The Cortex-A9 MPCore consists of between one and four Cortex-A9 processors and a Snoop Control Unit (SCU) and other peripherals.