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Arm Cortex‑R8 MPCore Processor Technical Reference Manual

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Arm® Cortex®‑R8 MPCore Processor Technical Reference Manual

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Introduction to the Technical Reference Manual

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Components of the   Cortex‑R8   processor

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Communication to the power management controller

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System identification, control, and configuration register

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Interface control and configuration registers

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Processor modes for accessing the FPU system registers

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Floating-Point Status and Control Register

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Clean and invalidate data cache by address

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Clean and invalidate data cache by set/way

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Memory types and L1 memory system behavior

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FPP Filtering Start Address Registers 0-3

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AXI protocol configurability, xIDSC, and AxUSERSC

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Debug Status and Control Register, DBGDSCR

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Device Powerdown and Reset Control Register, DBGPRCR

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Device Powerdown and Reset Status Register, DBGPRSR

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Breakpoint and Watchpoint Registers, DBGBVRn, DBGBCRn, DBGWVRn, and DBGWCRn

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  Cortex‑R8   processor ETM low-power control

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  Cortex‑R8   processor ETM register summary

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ViewData Include/Exclude Single Address Comparator Register

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ViewData Include/Exclude Address Range Comparator Register

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Sequencer State Transition Control Registers 0-2

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Single-Shot Comparator Control Registers 0-1

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Single-Shot Comparator Status Registers 0-1

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Address Comparator Access Type Registers 0-7

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Data Value Comparator Value Registers 0-1

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Data Value Comparator Mask Registers 0-1

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Context ID Comparator Control Register 0

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Output signals that the Integration Test Registers can control

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Input signals that the Integration Test Registers can read

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Integration Instruction ATB Data Register

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Integration Instruction ATB Out Register

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Read address channel of AXI master 0, ARUSERM0[9:0]

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Read address channel of AXI master 1, ARUSERM1[9:0]

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Read address bus of AXI low-latency peripheral, ARUSERMP[9:0]

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Write address channel of AXI master 0, AWUSERM0[11:0]

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Write address channel of AXI master 1, AWUSERM1[11:0]

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Write address bus of AXI low-latency peripheral, AWUSERMP[11:0]

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Write data channel of AXI master 0, WUSERM0[2:0]

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Write data channel of AXI master 1, WUSERM1[2:0]

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Write data bus of AXI low-latency peripheral, WUSERMP[2:0]

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Optimized accesses to the L2 memory interface

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Event communication with an external agent using WFE/SEV

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AXI master interface clock enable signals

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AXI master interface read address signals

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AXI master interface write address signals

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AXI master interface write response signals

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AXI fast peripheral clock enable signals

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AXI fast peripheral port read address signals

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AXI fast peripheral port read data signals

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AXI fast peripheral port write address signals

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AXI fast peripheral port write data signals

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AXI fast peripheral port write response signals

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AXI low-latency peripheral clock enable signals

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AXI low-latency peripheral port read address signals

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AXI low-latency peripheral port read data signals

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AXI low-latency peripheral port write address signals

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AXI low-latency peripheral port write data signals

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AXI low-latency peripheral port write response signals

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AXI ACP slave port write address signals

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AXI ACP slave port write response signals

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AXI TCM slave port write response signals

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Error detection global notification signals

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Bus ECC error signals on AXI master ports

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Bus ECC error signals on AXI fast peripheral port

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Bus ECC error signals on AXI low-latency peripheral port

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Bus ECC error signals on AXI ACP slave port

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Bus ECC error signals on AXI TCM slave port

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L1 and DTCM   Cortex‑R8   processor MBIST interface width without ECC

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L1 and DTCM   Cortex‑R8   processor MBIST interface width with ECC

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ITCM   Cortex‑R8   processor MBIST interface width without ECC

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ITCM   Cortex‑R8   processor MBIST interface width with ECC

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Single load and store operation cycle timings

# metadata.contentDescription
Arm Cortex ‑R8 MPCore Technical Reference Manual (TRM) providing reference information on the processor design, implementation, registers, and interfaces. The guide includes documentation on the Memory Protection Unit (MPU), interrupt controller, debug, level 1 and level 2 interfaces. Available as PDF.