# title
Arm Cortex-A32 Processor Technical Reference Manual r1p0

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Arm Cortex-A32 Processor Technical Reference Manual

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Clocks, Resets, and Input Synchronization

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Powering down the processor without system driven L2 flush

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Powering up the processor without system driven L2 flush

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Powering down the processor with system driven L2 flush

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Powering up the processor with system driven L2 flush

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Communication to the Power Management Controller

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Coherency between data caches with the MOESI protocol

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Cache misses, unexpected cache hits, and speculative fetches

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Memory type information exported from the processor

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AArch32 Virtual memory control registers

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Auxiliary Instruction Fault Status Register

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Auxiliary Memory Attribute Indirection Register 0

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Auxiliary Memory Attribute Indirection Register 1

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Architectural Feature Access Control Register

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DFSR with Short-descriptor translation table format

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DFSR with Long-descriptor translation table format

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Hyp Auxiliary Data Fault Status Syndrome Register

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Hyp Auxiliary Instruction Fault Status Syndrome Register

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Hyp Auxiliary Memory Attribute Indirection Register 0

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Hyp Auxiliary Memory Attribute Indirection Register 1

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IFSR with Short-descriptor translation table format

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IFSR with Long-descriptor translation table format

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Memory Attribute Indirection Registers 0 and 1

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TTBCR with Short-descriptor translation table format

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TTBCR with Long-descriptor translation table format

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TTBR0 with Short-descriptor translation table format

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TTBR0 with Long-descriptor translation table format

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TTBR1 with Short-descriptor translation table format

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TTBR1 with Long-descriptor translation table format

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Virtual interface control register summary

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VM CPU Interface Identification Register

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External access permissions to debug registers

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Changing the authentication signals for debug

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External register access permissions to the PMU registers

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Configuration options for the ETM unit and trace resources

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Programming and reading ETM trace unit registers

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Encoding for tag and data in the L1 instruction cache

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Encoding for tag and data in the L1 data cache

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TLB encoding for memory types and shareability

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External Debug Integration Mode Control Register

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External Debug Processor Feature Register

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External Debug AArch32 Processor Feature Register

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External Debug Peripheral Identification Register 0

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External Debug Peripheral Identification Register 1

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External Debug Peripheral Identification Register 2

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External Debug Peripheral Identification Register 3

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External Debug Peripheral Identification Register 4

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External Debug Peripheral Identification Register 5-7

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External Debug Component Identification Register 0

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External Debug Component Identification Register 1

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External Debug Component Identification Register 2

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External Debug Component Identification Register 3

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ROM Table Peripheral Identification Registers

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ROM Table Peripheral Identification Register 0

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ROM Table Peripheral Identification Register 1

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ROM Table Peripheral Identification Register 2

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ROM Table Peripheral Identification Register 3

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ROM Table Peripheral Identification Register 4

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ROM Table Peripheral Identification Register 5-7

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ROM Table Component Identification Registers

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ROM Table Component Identification Register 0

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ROM Table Component Identification Register 1

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ROM Table Component Identification Register 2

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ROM Table Component Identification Register 3

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Performance Monitors Common Event Identification Register 0

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Performance Monitors Common Event Identification Register 1

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Performance Monitors Peripheral Identification Register 0

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Performance Monitors Peripheral Identification Register 1

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Performance Monitors Peripheral Identification Register 2

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Performance Monitors Peripheral Identification Register 3

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Performance Monitors Peripheral Identification Register 4

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Performance Monitors Peripheral Identification Register 5-7

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Performance Monitors Component Identification Register 0

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Performance Monitors Component Identification Register 1

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Performance Monitors Component Identification Register 2

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Performance Monitors Component Identification Register 3

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Sequencer State Transition Control Registers 0-2

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Resource Selection Control Registers 2-16

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Single-Shot Comparator Control Register 0

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Single-Shot Comparator Status Register 0

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Address Comparator Access Type Registers 0-7

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Context ID Comparator Control Register 0

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Integration Instruction ATB Data Register

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Integration Instruction ATB Out Register

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ETM Peripheral Identification Register 0

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ETM Peripheral Identification Register 1

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ETM Peripheral Identification Register 2

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ETM Peripheral Identification Register 3

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ETM Peripheral Identification Register 4

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ETM Peripheral Identification Register 5-7

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External register access permissions to the CTI registers

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CTI Peripheral Identification Register 0

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CTI Peripheral Identification Register 1

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CTI Peripheral Identification Register 2

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CTI Peripheral Identification Register 3

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CTI Peripheral Identification Register 4

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CTI Peripheral Identification Register 5-7

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Broadcast signals for the memory interface

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UNPREDICTABLE instructions within an IT Block

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Load/Store accesses crossing page boundaries

# metadata.contentDescription
This Technical Reference Manual is for the Cortex-A32 processor. It provides reference documentation and contains programming details for registers. It also describes the memory system, the caches, the interrupts, and the debug features.