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Arm Cortex-M33 Devices Generic User Guide

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Arm® Cortex®-M33 Devices Generic User Guide

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About the Cortex-M33 processor and core peripherals

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Processor modes and privilege levels for software execution

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The Cortex Microcontroller Software Interface Standard

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Secure memory system and memory partitioning

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Additional memory access constraints for caches and shared memory

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Programming hints for the synchronization primitives

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Fault status registers and fault address registers

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Binary compatibility with other Cortex processors

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List of CMSIS functions to generate some processor instructions

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CMSIS functions to access the special registers

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CMSIS functions to access the Non-secure special registers

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List of multiply and divide instructions

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SMLAWB, SMLAWT, SMLABB, SMLABT, SMLATB, and SMLATT

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SMLALD, SMLALDX, SMLALBB, SMLALBT, SMLALTB, and SMLALTT

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List of packing and unpacking instructions

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VCVT and VCVTR between floating-point and integer

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VCVT between floating-point and fixed-point

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VMOV two core registers to two single-precision registers

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VMOV two core registers and a double-precision register

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VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ 

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Application Interrupt and Reset Control Register

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System Handler Control and State Register

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System control block design hints and tips

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Accessing the NVIC registers using CMSIS

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Hardware and software control of interrupts

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Security Attribution and  Memory Protection

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Security Attribution Unit Control Register

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Security Attribution Unit Region Number Register

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Security Attribution Unit Region Base Address Register

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Security Attribution Unit Region Limit Address Register

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MPU Region Base Address Register Alias, n=1-3

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MPU Region Limit Address Register Alias, n=1-3

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MPU Memory Attribute Indirection Registers 0 and 1

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Floating-point Default Status Control Register

# metadata.contentDescription
This book is a generic user guide for devices that implement the Arm Cortex -M33 processor. Implementers of Cortex-M33 designs make several implementation choices that can affect the functionality of the device. This means that, in this book some information is described as implementation-defined, and some features are described as optional. In this book, unless the context indicates otherwise, processor refers to the Cortex -M33 processor, as supplied by Arm , and device refers to an implemented device, which is supplied by an Arm partner, that incorporates a Cortex -M33 processor. In particular, your device refers to the particular implementation of the Cortex -M33 that you are using. Some features of your device depend on the implementation choices made by the Arm partner that made the device.