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Arm Cortex-M33 Processor Technical Reference Manual

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ARM ARMv8-R Architecture Reference Manual

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Arm® Cortex®-M33 Processor Technical Reference Manual

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Security attribution and memory protection

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Security Attribution and Memory Protection

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About security attribution and memory protection

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Configuring which coprocessors are included in Secure and Non-secure states

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Debug access to coprocessor registers usage constraints

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Debugger actions for identifying the processor

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Processor ROM table identification and entries

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Integration Mode Write ATB Valid Register

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Integration Mode Read ATB Ready Register

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AHB-AP Control/Status Word register, CSW, 0x00

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AHB-AP Transfer Address Register, TAR, 0x04

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AHB-AP Data Read/Write register, DRW, 0x0C

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AHB-AP Banked Data registers, BD0-BD03, 0x10-0x1C

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AHB-AP Debug Base Address register, ROM, 0xF8

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AHB-AP Configuration register, CFG, 0xF4

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AHB-AP Identification Register, IDR, 0xFC

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Debug Port Identification Register, DPIDR

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Read Buffer implementation and use on a JTAG-DP

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Read Buffer implementation and use on an SW-DP

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Data Link Control Register, DLCR (SW-DP only)

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Target Identification register, TARGETID (SW-DP only)

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Data Link Protocol Identification Register, DLPIDR (SW-DP only)

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Read Resend register, RESEND (SW-DP only)

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Integration Test FIFO Test Data 0 Register

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Integration Test FIFO Test Data 1 Register

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Use of instructions defined in architecture variants

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Use of Stack Pointer - as a general purpose register R13 

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Register list in load and store multiple instructions

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UNPREDICTABLE instructions within an IT block

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Load exclusive and Store exclusive accesses

# metadata.contentDescription
This book is for the Cortex®-M33 processor.